LTC2247 Linear Technology, LTC2247 Datasheet - Page 15

• Manufacturer Part Number: LTC2247
• Description: (LTC2246 - LTC2248) 65/40/25Msps Low Power 3V ADCs
• Manufacturer: Linear Technology

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APPLICATIO S I FOR ATIO
Input Drive Impedance
As with all high performance, high speed ADCs, the
dynamic performance of the LTC2248/LTC2247/LTC2246
can be influenced by the input drive circuitry, particularly
the second and third harmonics. Source impedance and
reactance can influence SFDR. At the falling edge of CLK,
the sample-and-hold circuit will connect the 4pF sampling
capacitor to the input pin and start the sampling period.
The sampling period ends when CLK rises, holding the
sampled input on the sampling capacitor. Ideally the input
circuitry should be fast enough to fully charge
the sampling capacitor during the sampling period
1/(2F
incomplete settling may degrade the SFDR. The sampling
glitch has been designed to be as linear as possible to
minimize the effects of incomplete settling.
For the best performance, it is recommended to have a
source impedance of 100Ω or less for each input. The
source impedance should be matched for the differential
inputs. Poor matching will result in higher even order
harmonics, especially the second.
Input Drive Circuits
Figure 3 shows the LTC2248/LTC2247/LTC2246 being
driven by an RF transformer with a center tapped second-
ary. The secondary center tap is DC biased with V
setting the ADC input signal at its optimum DC level.
Terminating on the transformer secondary is desirable, as
this provides a common mode path for charging glitches
caused by the sample and hold. Figure 3 shows a 1:1 turns
ratio transformer. Other turns ratios can be used if the
source impedance seen by the ADC does not exceed 100Ω
for each ADC input. A disadvantage of using a transformer
is the loss of low frequency response. Most small RF
transformers have poor performance at frequencies be-
low 1MHz.
Figure 4 demonstrates the use of a differential amplifier to
convert a single ended input signal into a differential input
signal. The advantage of this method is that it provides low
frequency input response; however, the limited gain band-
width of most op amps will limit the SFDR at high input
frequencies.
ENCODE
); however, this is not always possible and the
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CM
,
Figure 5 shows a single-ended input circuit. The imped-
ance seen by the analog inputs should be matched. This
circuit is not recommended if low distortion is required.
The 25Ω resistors and 12pF capacitor on the analog inputs
serve two purposes: isolating the drive circuitry from the
sample-and-hold charging glitches and limiting the
wideband noise at the converter input.
LTC2248/LTC2247/LTC2246
ANALOG
INPUT
ANALOG
INPUT
Figure 3. Single-Ended to Differential Conversion
ANALOG
INPUT
Figure 4. Differential Drive with an Amplifier
0.1µF
T1 = MA/COM ETC1-1T
RESISTORS, CAPACITORS
ARE 0402 PACKAGE SIZE
0.1µF
DIFFERENTIAL
Figure 5. Single-Ended Drive
CM
+
–
1:1
T1
HIGH SPEED
AMPLIFIER
Using a Transformer
–
+
1k
25Ω
25Ω
1k
0.1µF
25Ω
25Ω
25Ω
25Ω
0.1µF
25Ω
25Ω
12pF
2.2µF
2.2µF
12pF
V
A
A
V
A
A
2.2µF
12pF
CM
IN
IN
CM
IN
IN
V
+
–
A
A
+
–
CM
IN
IN
LTC2248/47/46
+
–
LTC2248/47/46
LTC2248/47/46
224876 F05
224876 F04
224876 F03
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