LTC2410 Linear Technology, LTC2410 Datasheet - Page 23

• Manufacturer Part Number: LTC2410
• Description: 24-Bit No Latency ADC with Differential Input and Differential Reference
• Manufacturer: Linear Technology

APPLICATIO S I FOR ATIO
Figure 21. Offset Error vs Common Mode Voltage
(V
( R
INCM
IN
Figure 19. +FS Error vs R
Figure 20. –FS Error vs R
= R
= IN
SOURCEIN
+
= IN
–120
–180
–240
–300
–100
–120
–60
–20
–40
–60
–80
300
240
180
120
120
100
80
60
40
20
60
0
0
0
–
0 100 200 300 400 500 600 700 800 900 1000
0 100 200 300 400 500 600 700 800 900 1000
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5
) and Input Source Resistance Imbalance
+ – R
A: R
B: R
C: R
D: R
V
REF
REF
IN
IN
F
T
V
REF
REF
IN
IN
F
T
O
A
O
A
CC
CC
+
–
+
–
U
= GND
= 25 C
= GND
= 25 C
IN
IN
IN
IN
A
B
C
D
E
F
G
+
= 3.75V
= 1.25V
+
–
= 1.25V
= 3.75V
SOURCEIN
–
= 5V
= 5V
= 5V
= 5V
= GND
= GND
= +400
= +200
= +100
= 0
V
REF
REF
IN
SOURCE
U
SOURCE
F
T
R
C
CC
R
R
+
O
A
IN
SOURCEIN
SOURCE
SOURCE
+
–
= IN
V
–) for Large C
= 5V
= GND
= 25 C
= 10 F
INCM
= 5V
= GND
–
C
C
C
= V
(V)
IN
IN
IN
at IN
at IN
( )
( )
– = 500
= 1 F, 10 F
INCM
= 0.01 F
= 1 F, 10 F
C
E: R
F: R
G: R
C
C
IN
W
IN
IN
+
+
= 0.01 F
= 0.1 F
= 0.1 F
or IN
or IN
IN
IN
IN
= –100
= –200
IN
= –400
Values (C
–
–
2410 F19
2410 F20
2410 F21
(Large C
(Large C
U
IN
IN
IN
)
)
1 F)
In addition to the input sampling charge, the input ESD
protection diodes have a temperature dependent leakage
current. This current, nominally 1nA ( 10nA max), results
in a small offset shift. A 100 source resistance will create
a 0.1 V typical and 1 V maximum offset voltage.
Reference Current
In a similar fashion, the LTC2410 samples the differential
reference pins REF
charge to and from the external driving circuits thus
producing a dynamic reference current. This current does
not change the converter offset but it may degrade the gain
and INL performance. The effect of this current can be
analyzed in the same two distinct situations.
For relatively small values of the external reference capaci-
tors (C
settles almost completely and relatively large values for
the source impedance result in only small errors. Such
values for C
gain performance without significant benefits of reference
filtering and the user is advised to avoid them.
Larger values of reference capacitors (C
be required as reference filters in certain configurations.
Such capacitors will average the reference sampling charge
and the external source resistance will see a quasi con-
stant reference differential impedance. When F
(internal oscillator and 60Hz notch), the typical differential
reference resistance is 1.3M which will generate a gain
error of approximately 0.38ppm for each ohm of source
resistance driving REF
oscillator and 50Hz notch), the typical differential refer-
ence resistance is 1.56M which will generate a gain error
of approximately 0.32ppm for each ohm of source resis-
tance driving REF
external oscillator with a frequency f
sion clock operation), the typical differential reference
resistance is 0.20 • 10
resistance drving REF
2.47 • 10
resistance on the two reference pins is additive with
respect to this gain error. The typical +FS and –FS errors
for various combinations of source resistance seen by the
REF
–6
< 0.01 F), the voltage on the sampling capacitor
• f
REF
EOSC
will deteriorate the converter offset and
ppm gain error. The effect of the source
+
+
and REF
or REF
+
12
or REF
/f
EOSC
+
–
–
. When F
transfering small amount of
or REF
–
. When F
and each ohm of source
EOSC
–
O
REF
O
LTC2410
(external conver-
= HIGH (internal
is driven by an
will result in
> 0.01 F) may
O
23
= LOW