LTC2439-1 Linear Technology, LTC2439-1 Datasheet - Page 23

• Manufacturer Part Number: LTC2439-1
• Description: 8-/16-Channel 16-Bit No Latency Delta-Sigma ADC
• Manufacturer: Linear Technology

APPLICATIO S I FOR ATIO
and each ohm of source resistance driving IN
result in 1.11 • 10
effect of the source resistance on the two input pins is
additive with respect to this gain error. The typical +FS and
–FS errors as a function of the sum of the source resis-
tance seen by IN
in Figures 16 and 17.
In addition to this gain error, an offset error term may also
appear. The offset error is proportional with the mismatch
between the source impedance driving the two input pins
IN
reference common mode voltages. While the input drive
circuit nonzero source impedance combined with the con-
verter average input current will not degrade the INL
performance, indirect distortion may result from the modu-
lation of the offset error by the common mode component
of the input signal. Thus, when using large C
values, it is advisable to carefully match the source imped-
ance seen by the IN
(internal oscillator and 50Hz/60Hz notch), every 60 mis-
match in source impedance transforms a full-scale com-
mon mode input signal into a differential mode input
signal of 1LSB. When F
with a frequency f
impedance transforms a full-scale common mode input
signal into a differential mode input signal of 1.11 • 10
• f
input common mode voltage for various values of source
resistance imbalance between the IN
large C
If possible, it is desirable to operate with the input signal
common mode voltage very close to the reference signal
common mode voltage as is the case in the ratiometric
measurement of a symmetric bridge. This configuration
eliminates the offset error caused by mismatched source
impedances.
The magnitude of the dynamic input current depends upon
the size of the very stable internal sampling capacitors and
upon the accuracy of the converter sampling clock. The
accuracy of the internal clock over the entire temperature
and power supply range is typically better than 0.5%. Such
a specification can also be easily achieved by an external
clock. When relatively stable resistors (50ppm/ C) are
used for the external source impedance seen by IN
EOSC
+
and IN
LSB. Figure 18 shows the typical offset error due to
IN
values are used.
–
and with the difference between the input and
+
–7
and IN
EOSC
U
• f
+
EOSC
O
–
and IN
, every 1
is driven by an external oscillator
for large values of C
U
LSB gain error at full scale. The
–
pins. When F
W
mismatch in source
+
and IN
IN
–
+
IN
U
are shown
pins when
or IN
O
capacitor
= LOW
+
–
and
will
–7
Figure 17. –FS Error vs R
Figure 16. +FS Error vs R
Figure 18. Offset Error vs Common Mode Voltage
(V
Imbalance ( R
Large C
INCM
–12
–16
–20
–4
–8
20
16
12
–4
–8
= IN
8
4
0
0
8
4
0
IN
0 100 200 300 400 500 600 700 800 900 1000
0 100 200 300 400 500 600 700 800 900 1000
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5
A: R
B: R
C: R
D: R
Values (C
V
REF
REF
IN
IN
F
T
V
REF
REF
IN
IN
F
T
O
A
O
+
CC
A
CC
+
–
+
–
= GND
= 25 C
= GND
= 25 C
= IN
+
= 3.75V
= 1.25V
–
+
–
= 1.25V
= 3.75V
= 5V
= 5V
IN
IN
IN
IN
A
B
C
D
E
F
G
= 5V
= GND
= 5V
= GND
IN
= +400
= +200
= +100
= 0
–
= R
) and Input Source Resistance
IN
V
REF
REF
IN
SOURCEIN
F
T
R
C
CC
SOURCE
SOURCE
R
R
+
O
A
IN
SOURCEIN
SOURCE
SOURCE
+
= IN
V
–
= GND
= 25 C
= 5V
= 10 F
INCM
1 F)
= 5V
= GND
–
C
C
C
= V
IN
IN
(V)
IN
( )
( )
at IN
at IN
– = 500
+ – R
= 1 F, 10 F
INCM
= 0.01 F
= 1 F, 10 F
C
E: R
F: R
G: R
C
C
IN
IN
IN
LTC2439-1
+
= 0.01 F
+
= 0.1 F
= 0.1 F
SOURCEIN
IN
IN
or IN
or IN
IN
= –200
= –100
= –400
24361 F16
24361 F17
24361 F18
–
–
(Large C
(Large C
–) for
23
IN
IN
)
)
24391f