LTC2497 Linear Technology, LTC2497 Datasheet - Page 17

• Manufacturer Part Number: LTC2497
• Description: 16-Bit 8-/16-Channel ADC
• Manufacturer: Linear Technology

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APPLICATIONS INFORMATION
Initiating a New Conversion
When the LTC2497 fi nishes a conversion, it automatically
enters the sleep state. Once in the sleep state, the device is
ready for a read operation. After the device acknowledges
a read request, the device exits the sleep state and enters
the data output state. The data output state concludes
and the LTC2497 starts a new conversion once a Stop
condition is issued by the master or all 24 bits of data are
read out of the device.
During the data read cycle, a Stop command may be issued
by the master controller in order to start a new conversion
and abort the data transfer. This Stop command must be
issued during the ninth clock cycle of a byte read when
the bus is free (the ACK/NAK cycle).
LTC2497 Address
The LTC2497 has three address pins (CA0, CA1, CA2).
Each may be tied high, low, or left fl oating enabling one
of 27 possible addresses (see Table 4).
In addition to the confi gurable addresses listed in Table 4,
the LTC2497 also contains a global address (1110111)
which may be used for synchronizing multiple LTC2497s
or other LTC24XX delta-sigma I
chronizing Multiple LTC2497s with Global Address Call
section).
Operation Sequence
The LTC2497 acts as a transmitter or receiver, as shown
in Figure 4. The device may be programmed to select
an input channel, differential or single-ended mode, and
channel polarity.
Continuous Read
In applications where the input channel does not need to
change for each cycle, the conversion can be continuously
performed and read without a write cycle (see Figure 5).
The input channel remains unchanged from the last
value written into the device. If the device has not been
written to since power up, the channel selection is set to
the default value of CH0 = IN
a read operation, a new conversion automatically begins.
At the conclusion of the conversion cycle, the next result
+
, CH1 = IN
2
C devices, (See Syn-
–
. At the end of
Table 4. Address Assignment
may be read using the method described above. If the
conversion cycle is not concluded and a valid address
selects the device, the LTC2497 generates a NAK signal
indicating the conversion cycle is in progress.
Continuous Read/Write
Once the conversion cycle is concluded, the LTC2497 can
be written to and then read from using the Repeated Start
(Sr) command.
Figure 6 shows a cycle which begins with a data Write,
a repeated Start, followed by a Read and concluded with
FLOAT
FLOAT
FLOAT
FLOAT
FLOAT
FLOAT
FLOAT
FLOAT
FLOAT
HIGH
HIGH
HIGH
HIGH
HIGH
HIGH
HIGH
HIGH
HIGH
LOW
LOW
LOW
LOW
LOW
LOW
LOW
LOW
LOW
CA2
FLOAT
FLOAT
FLOAT
FLOAT
FLOAT
FLOAT
FLOAT
FLOAT
FLOAT
HIGH
HIGH
HIGH
HIGH
HIGH
HIGH
HIGH
HIGH
HIGH
LOW
LOW
LOW
LOW
LOW
LOW
LOW
LOW
LOW
CA1
FLOAT
FLOAT
FLOAT
FLOAT
FLOAT
FLOAT
FLOAT
FLOAT
FLOAT
HIGH
HIGH
HIGH
HIGH
HIGH
HIGH
HIGH
HIGH
HIGH
LOW
LOW
LOW
LOW
LOW
LOW
LOW
LOW
LOW
CA0
LTC2497
ADDRESS
0010100
0010110
0010101
0100110
0110100
0100111
0010111
0100101
0100100
1010110
1100100
1010111
1110100
1110110
1110101
1100101
1100111
1100110
0110101
0110111
0110110
1000111
1010101
1010100
1000100
1000110
1000101
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