LTC2600 Linear Technology, LTC2600 Datasheet - Page 10

• Manufacturer Part Number: LTC2600
• Description: (LTC2600 - LTC2620) 3V/5V Octal 12-bit Rail-to-rail DAC
• Manufacturer: Linear Technology

OPERATIO
LTC2600/LTC2610/LTC2620
Power-On Reset
The LTC2600/LTC2610/LTC2620 clear the outputs to zero
scale when power is first applied, making system initializa-
tion consistent and repeatable.
For some applications, downstream circuits are active
during DAC power-up, and may be sensitive to nonzero
outputs from the DAC during this time. The LTC2600/
LTC2610/LTC2620 contain circuitry to reduce the power-
on glitch; furthermore, the glitch amplitude can be made
arbitrarily small by reducing the ramp rate of the power
supply. For example, if the power supply is ramped to 5V
in 1ms, the analog outputs rise less than 10mV above
ground (typ) during power-on. See Power-On Reset Glitch
in the Typical Performance Characteristics section.
Power Supply Sequencing
The voltage at REF (Pin 6) should be kept within the range
– 0.3V
Ratings). Particular care should be taken to observe these
limits during power supply turn-on and turn-off sequences,
when the voltage at V
Transfer Function
The transfer function is
Table 1.
COMMAND
10
C3 C2 C1 C0
0
0
0
0
0
1
V
OUT IDEAL
0
0
0
0
1
1
(
0
0
1
1
0
1
V
REF
0
1
0
1
0
1
)
U
Write to Input Register n
Update (Power-Up) DAC Register n
Write to Input Register n, Update (Power Up) All
Write to and Update (Power Up) n
Power Down n
No Operation
V
2
CC
k
N
CC
+ 0.3V (see Absolute Maximum
V
REF
(Pin 16) is in transition.
where k is the decimal equivalent of the binary DAC input
code, N is the resolution and V
(Pin 6).
Serial Interface
Referring to Figure 2a: The CS/LD input is level triggered.
When this input is taken low, it acts as a chip-select signal,
powering-on the SDI and SCK buffers and enabling the
input shift register. Data (SDI input) is transferred at the
next 24 rising SCK edges. The 4-bit command word, C3-
C0, is loaded first; then the 4-bit DAC address, A3-A0; and
finally the 16-bit data word. The data word comprises the
16-, 14- or 12-bit input code, ordered MSB-to-LSB, fol-
lowed by 0, 2 or 4 don’t-care bits (LTC2600, LTC2610 and
LTC2620 respectively). Data can only be transferred to the
device when the CS/LD signal is low.The rising edge of
CS/LD ends the data transfer and causes the device to
carry out the action specified in the 24-bit input word. The
complete sequence is shown in Figure 2a; the command
(C3-C0) and address (A3-A0) assignments are shown in
Table 1.
Optionally, the instruction may be extended to 32 bits. To
use the 32-bit word width, 8 don’t-care bits are transferred
to the device first, followed by the 24-bit input word as just
described (see Figure 2b). The 32-bit word width is
required for daisy-chain operation, and is also available to
accommodate microprocessors which have a minimum
word width of 2 bytes.
ADDRESS (n)
A3 A2 A1 A0
0
0
0
0
0
0
0
0
1
0
0
0
0
1
1
1
1
1
0
0
1
1
0
0
1
1
1
0
1
0
1
0
1
0
1
1
DAC A
DAC B
DAC C
DAC D
DAC E
DAC F
DAC G
DAC H
All DACs
REF
is the voltage at REF
2600f