LTC2654 Linear Technology, LTC2654 Datasheet - Page 20

• Manufacturer Part Number: LTC2654
• Description: Quad 16-/12-Bit Rail-to-Rail DACs
• Manufacturer: Linear Technology

LTC2654
OPERATION
Integrated Reference Buffers
Each of the four DACs in the LTC2654 has its own inte-
grated high performance reference buffer. The buffers have
very high input impedance and do not load the reference
voltage source. These buffers shield the reference voltage
from glitches caused by DAC switching and thus minimize
DAC-to-DAC Dynamic Crosstalk. Typically DAC-to-DAC
crosstalk is less than 3nV•s. By tying 0.22μF capacitors
between REFCOMP and GND, and also between REFIN/
OUT and GND, this number can be reduced to less than
1nV•s. See the curve DAC-to-DAC Dynamic Crosstalk in
the Typical Performance Characteristics section.
Voltage Outputs
Each of the LTC2654’s four rail-to-rail output amplifi ers con-
tained in these parts has guaranteed load regulation when
sourcing or sinking up to 15mA at 5V (7.5mA at 3V).
Load regulation is a measure of the amplifi er’s ability to
maintain the rated voltage accuracy over a wide range of
load conditions. The measured change in output voltage
per milliampere of forced load current change is expressed
in LSB/mA.
DC output impedance is equivalent to load regulation, and
may be derived from it by simply calculating a change in
units from LSB/mA to Ohms. The amplifi ers’ DC output
impedance is 0.04Ω when driving a load well away from
the rails.
When drawing a load current from either rail, the output
voltage headroom with respect to that rail is limited by
the 30Ω typical channel resistance of the output devices;
e.g., when sinking 1mA, the minimum output voltage =
30Ω • 1mA = 30mV. See the graph Headroom at Rails vs
Output Current in the Typical Performance Characteristics
section.
The amplifi ers are stable driving capacitive loads of up
to 1000pF .
20
Board Layout
The excellent load regulation and DC crosstalk performance
of these devices is achieved in part by keeping signal and
power grounds separate.
The PC board should have separate areas for the analog
and digital sections of the circuit. This keeps digital signals
away from sensitive analog signals and facilitates the use
of separate digital and analog ground planes which have
minimal capacitive and resistive interaction with each
other.
Digital and analog ground planes should be joined at only
one point, establishing a system star ground as close to
the device’s ground pin as possible. Ideally, the analog
ground plane should be located on the component side of
the board, and should be allowed to run under the part to
shield it from noise. Analog ground should be a continuous
and uninterrupted plane, except for necessary lead pads
and vias, with signal traces on another layer.
The GND pin functions as a return path for power supply
currents in the device and should be connected to analog
ground. The REFLO pin should be connected to system
star ground. Resistance from the REFLO pin to system
star ground should be as low as possible.
Rail-to-Rail Output Considerations
In any rail-to-rail voltage output device, the output is limited
to voltages within the supply range.
Since the analog outputs of the device cannot go below
ground, they may limit for the lowest codes as shown in
Figure 3b. Similarly, limiting can occur in external refer-
ence mode near full-scale when the REFIN/OUT pin is at
V
(FSE) is positive, the output for the highest codes limits
at V
occur if V
Offset and linearity are defi ned and tested over the region
of the DAC transfer function where no output limiting can
occur.
CC
/2. If V
CC
as shown in Figure 3c. No full-scale limiting can
REFIN/OUT
REFIN/OUT
≤ (V
= V
CC
CC
/2 and the DAC full-scale error
– FSE)/2.
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