LTC2656 Linear Technology Corporation, LTC2656 Datasheet - Page 18

• Manufacturer Part Number: LTC2656
• Description: Octal 16-/12-Bit Rail-to-Rail DACs
• Manufacturer: Linear Technology Corporation

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LTC2656
The 4-bit command, C3-C0, is loaded fi rst; followed by the
4-bit DAC address, A3-A0; and fi nally the 16-bit data word.
For the LTC2656-16 the data word comprises the 16-bit
input code, ordered MSB-to-LSB. For the LTC2656-12 the
data word comprizes the 12-bit input code, ordered MSB-
to-LSB, followed by four don’t care bits. Data can only be
transferred to the LTC2656 when the CS/LD signal is low.
The rising edge of CS/LD ends the data transfer and causes
the device to carry out the action specifi ed in the 24-bit input
word. The complete sequence is shown in Figure 2a.
The command (C3-C0) and address (A3-A0) assignments
are shown in Table 1. The fi rst four commands in the table
consist of write and update operations. A write operation
loads a 16-bit data word from the 32-bit shift register
into the input register of the selected DAC, n. An update
operation copies the data word from the input register to
the DAC register. Once copied into the DAC register, the
data word becomes the active 16- or 12-bit input code,
and is converted to an analog voltage at the DAC output.
The update operation also powers up the selected DAC
if it had been in power-down mode. The data path and
registers are shown in the Block Diagram.
While the minimum input word is 24 bits, it may option-
ally be extended to 32 bits. To use the 32-bit word width,
8 don’t-care bits must be transferred to the device fi rst,
followed by the 24-bit word as just described. Figure 2b
shows the 32-bit sequence. The 32-bit word is required for
daisy-chain operation, and is also available to accommodate
microprocessors that have a minimum word width of 16 bits
(2 bytes). The 16-bit data word is ignored for all commands
that do not include a write operation.
Daisy-Chain Operation
The serial output of the shift register appears at the SDO pin.
Data transferred to the device from the SDI input is delayed
32 SCK rising edges before being output at the next SCK
falling edge. The SDO pin is continuously driven and does
not go high impedance when CS/LD is taken active high.
The SDO output can be used to facilitate control of multiple
serial devices from a single 3-wire serial port (i.e., SCK,
SDI and CS/LD). Such a “daisy-chain” series is confi gured
by connecting SDO of each upstream device to SDI of the
next device in the chain. The shift registers of the devices
OPERATION
18
are thus connected in series, effectively forming a single
input shift register which extends through the entire
chain. Because of this, the devices can be addressed and
controlled individually by simply concatenating their input
words; the fi rst instruction addresses the last device in
the chain and so forth. The SCK and CS/LD signals are
common to all devices in the series.
In use, CS/LD is fi rst taken low. Then the concatenated
input data is transferred to the chain, using SDI of the
fi rst device as the data input. When the data transfer is
complete, CS/LD is taken high, completing the instruction
sequence for all devices simultaneously. A single device
can be controlled by using the no-operation command
(1111) for the other devices in the chain.
Power-Down Mode
For power-constrained applications, power-down mode
can be used to reduce the supply current whenever
less than eight DAC outputs are needed. When in power
down, the buffer amplifi ers, bias circuits and integrated
reference circuits are disabled and draw essentially zero
current. The DAC outputs are put into a high impedance
state, and the output pins are passively pulled to ground
through individual 80k resistors. Input- and DAC-register
contents are not disturbed during power down.
Any channel or combination of DAC channels can be put
into power-down mode by using command 0100b in
combination with the appropriate DAC address, (n). The
integrated reference is automatically powered down when
external reference is selected using command 0111b. In
addition, all the DAC channels and the integrated refer-
ence together can be put into power-down mode using
power-down chip command 0101b. For all power-down
commands the 16-bit data word is ignored.
Normal operation resumes by executing any command
which includes a DAC update, in software as shown in
Table 1 or by taking the asynchronous LDAC pin low. The
selected DAC is powered up as its voltage output is up-
dated. When a DAC which is in a powered-down state is
powered up and updated, normal settling is delayed. If less
than eight DACs are in a powered-down state prior to the
update command, the power-up delay time is 12μs. If, on
the other hand, all eight DACs and the integrated reference
2656p