LTC2932 Linear Technology, LTC2932 Datasheet - Page 11

• Manufacturer Part Number: LTC2932
• Description: Confi gurable Six Supply Monitor
• Manufacturer: Linear Technology

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APPLICATIONS INFORMATION
Using the Adjustable Thresholds
The reference inputs on the V3 and/or V4 comparators
are set to 0.5V when the positive adjustable modes are
selected (Figure 3). The reference inputs on the V5 and V6
comparators are always set to 0.5V. The tap point on an
external resistive divider, connected between the positive
voltage being sensed and ground, is connected to the high
impedance, adjustable inputs (V3, V4, V5, V6). Calculate
the trip voltage from:
In the negative adjustable mode, the reference level on the
V4 comparator is connected to ground (Figure 4). The tap
point on an external resistive divider, connected between
the negative voltage being sensed and the VREF pin, is
connected to the high impedance adjustable input (V4).
V
at ground. The negative trip voltage is calculated from:
Once the resistor divider is set in the 5% tolerance mode,
there is no need to change the divider for the other toler-
ance modes (7.5%, 10%, 12.5%) because V
accordingly, moving the trip point in –2.5% increments.
In a negative adjustable application, the minimum value for
R4 is limited by the sourcing capability of VREF (±1mA).
With no other load on VREF , R4 (minimum) is:
Tables 3 and 4 offer suggested 1% resistor values for vari-
ous positive and negative supply adjustable applications
assuming 5% monitor thresholds.
REF
T0, T1 Low (5% Tolerance Mode)
V
V
1.210V
TRIP
TRIP
1mA
provides the necessary level shift required to operate
= 0.5V • 1+
= −V
= 1.210kΩ
REF
•
R3
R4
R3
R4
; V
REF
= 1.210V Nominal
REF
is scaled
Although all six supply monitor comparators have built-
in glitch immunity, bypass capacitors on V1 and V2 are
recommended because the greater of V1 or V2 is also the
V
V6 inputs are allowed.
Power-Down
On power-down, once any of the monitor inputs drops
below its threshold, RST is held at a logic low. A logic low
of 0.4V is guaranteed until both V1 and V2 drop below
1V. If the bandgap reference becomes invalid (V
typical), the LTC2932 will enter the 150μs setup period
when V
Selecting the Reset Timing Capacitor
The reset timeout period is adjustable in order to
accommodate a variety of microprocessor applications.
The reset timeout period, t
a capacitor, C
value of this capacitor is determined by:
Leaving the CRT pin unconnected generates a minimum
reset timeout of approximately 25μs. Maximum reset
timeout is limited by the largest available low leakage
capacitor. The accuracy of the timeout period is affected
by capacitor leakage (the nominal charging current is 2μA)
and capacitor tolerance. A low leakage ceramic capacitor
is recommended.
Reset Disable
Under conventional operation, RST and COMP
when V
can be pulled low, overriding the reset operation and forcing
the RST pin high. This feature is useful when determining
supply margins under processor control since the reset
command will not be invoked. The RDIS pin is connected
to a weak internal pull-up to V
the pin to be left open if unused.
CC
C
for the device. Filter capacitors on the V3, V4, V5 and
RT
=
n
CC
is below its threshold. At any time, the RDIS pin
2MΩ
t
rises above 2.4V (max).
RST
RT
= 500 pF / ms
, between the CRT pin and ground. The
[
RST
, is adjusted by connecting
CC
]
• t
(10μA typical), allowing
RST
LTC2932
n
will go low
CC
11
< 2V
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