LTC3405 Linear Technology, LTC3405 Datasheet - Page 10

• Manufacturer Part Number: LTC3405
• Description: Dual DC/DC Converter with USB Power Manager and Li-Ion Battery Charger
• Manufacturer: Linear Technology

www.DataSheet4U.com
APPLICATIO S I FOR ATIO
LTC3405
In pulse skipping mode, the LTC3405 is stable with a 4.7 F
ceramic output capacitor with V
applications operating in pulse skipping mode, the circuit
shown in Figure 6 can be used
When choosing the input and output ceramic capacitors,
choose the X5R or X7R dielectric formulations. These
dielectrics have the best temperature and voltage charac-
teristics of all the ceramics for a given value and size.
Output Voltage Programming
The output voltage is set by a resistive divider according
to the following formula:
The external resistive divider is connected to the output,
allowing remote voltage sensing as shown in Figure 7.
Efficiency Considerations
The efficiency of a switching regulator is equal to the
output power divided by the input power times 100%. It is
often useful to analyze individual losses to determine what
is limiting the efficiency and which change would produce
the most improvement. Efficiency can be expressed as:
where L1, L2, etc. are the individual losses as a percentage
of input power.
10
Figure 6. Using All Ceramic Capacitors in Pulse Skipping Mode
Efficiency = 100% – (L1 + L2 + L3 + ...)
TO 4.2V
V
OUT
2.7V
V
IN
Figure 7. Setting the LTC3405 Output Voltage
0 8 1
.
C
2.2 F
CER
IN
V
LTC3405
4
1
6
U
V
RUN
MODE
R
R
IN
LTC3405
2
1
GND
V
GND
FB
2
U
SW
V
FB
3
5
IN
0.8V V
1M
3405 F06
4.7 H
W
4.2V. For single Li-Ion
22pF
887k
OUT
R2
R1
3405 F07
5.5V
U
C
4.7 F
CER
OUT1
V
1.5V
OUT
(2)
Although all dissipative elements in the circuit produce
losses, two main sources usually account for most of the
losses in LTC3405 circuits: V
losses. The V
efficiency loss at very low load currents whereas the I
loss dominates the efficiency loss at medium to high load
currents. In a typical efficiency plot, the efficiency curve at
very low load currents can be misleading since the actual
power lost is of no consequence as illustrated in Figure 8.
1. The V
2. I
the DC bias current as given in the electrical character-
istics and the internal main switch and synchronous
switch gate charge currents. The gate charge current
results from switching the gate capacitance of the
internal power MOSFET switches. Each time the gate is
switched from high to low to high again, a packet of
charge, dQ, moves from V
dQ/dt is the current out of V
the DC bias current. In continuous mode, I
f(Q
internal top and bottom switches. Both the DC bias and
gate charge losses are proportional to V
their effects will be more pronounced at higher supply
voltages.
internal switches, R
continuous mode, the average output current flowing
through inductor L is “chopped” between the main
switch and the synchronous switch. Thus, the series
resistance looking into the SW pin is a function of both
2
R losses are calculated from the resistances of the
T
+ Q
IN
0.0001
0.001
0.01
quiescent current is due to two components:
B
0.1
) where Q
Figure 8. Power Lost vs Load Current
1
0.1
V
V
IN
IN
OUT
= 3.6V
quiescent current loss dominates the
= 2.5V
1
LOAD CURRENT (mA)
V
T
OUT
V
and Q
OUT
SW
= 1.8V
= 1.3V
, and external inductor R
10
B
IN
IN
IN
are the gate charges of the
quiescent current and I
that is typically larger than
to ground. The resulting
V
OUT
100
= 3.3V
3405 F08
1000
IN
GATECHG
and thus
sn3405 3405fs
L
. In
2
2
R
R
=