LTC3788-1 Linear Technology, LTC3788-1 Datasheet - Page 21

• Manufacturer Part Number: LTC3788-1
• Description: Dual Output Synchronous Boost Controller
• Manufacturer: Linear Technology

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APPLICATIONS INFORMATION
Effi ciency Considerations
The percent effi ciency of a switching regulator is equal to
the output power divided by the input power times 100%.
It is often useful to analyze individual losses to determine
what is limiting the effi ciency and which change would
produce the greatest improvement. Percent effi ciency
can be expressed as:
where L1, L2, etc., are the individual losses as a percent-
age of input power.
Although all dissipative elements in the circuit produce
losses, four main sources usually account for most of
the losses in LTC3788-1 circuits: 1) IC V
TV
transition losses.
1. The V
2. INTV
3. DC I
4. Transition losses apply only to the bottom MOSFET(s),
Other hidden losses, such as copper trace and internal
battery resistances, can account for an additional 5% to
Electrical Characteristics table, which excludes MOSFET
driver and control currents. V
in a small (<0.1%) loss.
control currents. The MOSFET driver current results
from switching the gate capacitance of the power MOS-
FETs. Each time a MOSFET gate is switched from low to
high to low again, a packet of charge, dQ, moves from
INTV
of INTV
circuit current. In continuous mode, I
Q
and bottom side MOSFETs.
the MOSFETs, sensing resistor, inductor and PC board
traces and cause the effi ciency to drop at high output
currents.
and become signifi cant only when operating at low input
voltages (typically 15V or greater). Transition losses can
be estimated from:
CC
%Effi ciency = 100% – (L1 + L2 + L3 + ...)
Transition Loss
B
), where Q
regulator current, 3) I
CC
CC
2
IN
R losses. These arise from the resistances of
CC
to ground. The resulting dQ/dt is a current out
current is the sum of the MOSFET driver and
current is the DC supply current given in the
that is typically much larger than the control
T
and Q
= ( . )
B
are the gate charges of the topside
1 7
2
R losses, 4) Bottom MOSFET
IN
V
OUT
V
current typically results
IN
3
I
IN
O MAX
GATECHG
(
current, 2) IN-
)
•
= f(Q
C
RSS
T
f
+
10% effi ciency degradation in portable systems. It is very
important to include these system-level losses during the
design phase.
Checking Transient Response
The regulator loop response can be checked by looking at
the load current transient response. Switching regulators
take several cycles to respond to a step in DC (resistive)
load current. When a load step occurs, V
amount equal to ΔI
series resistance of C
or discharge C
that forces the regulator to adapt to the current change and
return V
time V
or ringing, which would indicate a stability problem.
OPTI-LOOP compensation allows the transient response
to be optimized over a wide range of output capacitance
and ESR values. The availability of the ITH pin not only
allows optimization of control loop behavior, but it also
provides a DC coupled and AC fi ltered closed loop response
test point. The DC step, rise time and settling at this test
point truly refl ects the closed loop response. Assuming a
predominantly second order system, phase margin and/or
damping factor can be estimated using the percentage of
overshoot seen at this pin. The bandwidth can also be
estimated by examining the rise time at the pin. The I
external components shown in Figure 9 circuit will provide
an adequate starting point for most applications.
The I
loop compensation. The values can be modifi ed slightly
(from 0.5 to 2 times their suggested values) to optimize
transient response once the fi nal PC layout is complete
and the particular output capacitor type and value have
been determined. The output capacitors must be selected
because the various types and values determine the loop
gain and phase. An output current pulse of 20% to 80%
of full-load current having a rise time of 1μs to 10μs will
produce output voltage and ITH pin waveforms that will
give a sense of the overall loop stability without breaking
the feedback loop.
Placing a power MOSFET and load resistor directly across
the output capacitor and driving the gate with an ap-
propriate signal generator is a practical way to produce
TH
OUT
OUT
series RC-CC fi lter sets the dominant pole-zero
can be monitored for excessive overshoot
to its steady-state value. During this recovery
OUT
LOAD
generating the feedback error signal
OUT
(ESR), where ESR is the effective
. ΔI
LOAD
also begins to charge
LTC3788-1
OUT
shifts by an
21
37881f
TH