LTC4001-1 Linear Technology, LTC4001-1 Datasheet - Page 15

• Manufacturer Part Number: LTC4001-1
• Description: 2A Synchronous Buck Li-Ion Charger
• Manufacturer: Linear Technology

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APPLICATIONS INFORMATION
to V
as the V
voltage drop in the LTC4001-1 is very low when charge
current is highest, power dissipation is also very low.
Thermal Calculations (PWM and Trickle Charging)
The LTC4001-1 operates as a linear charger when condition-
ing (trickle) charging a battery and operates as a high rate
buck battery charger at all other times. Power dissipation
should be determined for both operating modes.
For linear charger mode:
where I
Worst-case dissipation occurs for V
V
For example with 5.5V maximum input voltage and 65mA
worst case trickle charge current, and 2mA worst case
chip quiescent current:
LTC4001-1 power dissipation is very low if a current
limited wall adapter is used and allowed to enter current
limit. When the wall adapter is in current limit, the voltage
drop across the LTC4001-1 charger is:
where I
the on resistance of the topside PMOS switch.
IN
P
P
V
, and maximum quiescent and trickle charge current.
ADAPTER
D
D
DROP
= (V
= (5.5 – 0) • 65mA + 5.5 • 2mA = 368.5mW
IN
LIMIT
BAT
= I
is V
IN
rises, dropping to zero at V
. Battery charging current continues to drop
LIMIT
– V
is the wall adapter current limit and R
IN
BAT
current consumed by the IC.
• R
) • I
PFET
TRIKL
I
V
BAT
IN
+ V
IN
• I
LINEAR CHARGING
IN
BAT
V
FLOAT.
I
ADAPTER
TRICKLE
= 0, maximum
Figure 5. Charging Characteristic
Because the
PFET
V
TRIKL
is
WALL ADAPTER IN CURRENT LIMIT
V
BAT
The total LTC4001-1 power dissipation during current
limited charging is:
where I
rent fl owing through the IDET and PROG programming
pins. Maximum dissipation in this mode occurs with the
highest V
(which is very close to V
I
highest programming current I
Assume the LTC4001-1 is programmed for 2A charging and
200mA IDET and that a 1.5A wall adapter is being used:
then:
and:
Power dissipation in buck battery charger mode may be
estimated from the dissipation curves given in the Typical
Performance Characteristics section of the data sheet.
This will slightly overestimate chip power dissipation
because it assumes all loss, including loss from external
components, occurs within the chip.
IN
, highest PMOS on resistance R
V
P
I
and V
V
P
• 1500mA = 312mW
BAT
LIMIT
D
DROP
D
I
LIMIT
+ V
= (V
= (4.141V + 0.1905V) • (2mA + 4mA) + 0.1905V
IN
DROP
BAT
= 1500mA, R
BAT
= 1500mA • 127mΩ = 190.5mV
is the chip quiescent current and I
BAT
≈ V
that keeps the wall adapter in current limit
+ V
FLOAT
DROP
V
CHARGING
= 4.141V
FLOAT
PFET
) • (I
PWM
FLOAT
40011 F05
= 127mΩ, I
IN
+ I
), highest quiescent current
P
P
.
) + V
PFET
LTC4001-1
IN
, highest I
DROP
= 2mA, I
• I
P
is total cur-
LIMIT
LIMIT
P
15
= 4mA
40011fa
and