LTC4440 Linear Technology, LTC4440 Datasheet - Page 6

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LTC4440

Manufacturer Part Number
LTC4440
Description
High Speed High Voltage High Side Gate Driver
Manufacturer
Linear Technology
Datasheet

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PI FU CTIO S
BLOCK DIAGRA
LTC4440
Exposed Pad MS8E Package
INP (Pin 1): Input Signal. TTL/CMOS compatible input
referenced to GND (Pin 2).
GND (Pins 2, 4): Chip Ground.
V
side circuitry. A low ESR ceramic bypass capacitor should
be tied between this pin and the GND pin (Pin 2).
NC (Pin 5): No Connect. No connection required. For
convenience, this pin may be tied to Pin 6 (BOOST) on the
application board.
6
TI I G DIAGRA
CC
U
W
(Pin 3): Chip Supply. This pin powers the internal low
U
U
8V TO 15V
U
W
V
GND
INP
W
CC
UNDERVOLTAGE
OUTPUT (TG)
LOCKOUT
INPUT (INP)
UNDERVOLTAGE
V
INPUT RISE/FALL TIME < 10ns
HIGH SIDE
LOCKOUT
IH
t
PLH
t
r
LEVEL SHIFTER
GND
BOOST (Pin 6): High Side Bootstrapped Supply. An exter-
nal capacitor should be tied between this pin and TS
(Pin 8). Normally, a bootstrap diode is connected between
V
V
drop of the bootstrap diode.
TG (Pin 7): High Current Gate Driver Output (Top Gate).
This pin swings between TS and BOOST.
TS (Pin 8): Top (High Side) Source Connection.
Exposed Pad (Pin 9): Ground. Must be electrically con-
nected to Pins 2 and 4 and soldered to PCB ground for
optimum thermal performance.
CC
CC
– V
(Pin 3) and this pin. Voltage swing at this pin is from
t
PHL
BOOST
TS
D
V
t
IL
to V
f
IN
90%
10%
+ V
4440 TD
BOOST
CC
– V
TG
TS
D
, where V
UP TO 100V
UP TO 80V,
TRANSIENT
www.DataSheet4U.com
D
V
is the forward voltage
IN
4440 BD
4440f

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