FS6054 AMI, FS6054 Datasheet
FS6054
Related parts for FS6054
FS6054 Summary of contents
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... Serial interface I/O meet I I/O are LVTTL/LVCMOS-compatible Five differerent pin configurations available: FS6050: 18 clock outputs in a 48-pin SSOP FS6051: 10 clock outputs in a 28-pin SOIC, SSOP FS6053: 13 clock outputs in a 28-pin SOIC FS6054: 14 clock outputs in a 28-pin SOIC Figure 1: Block Diagram (FS6050) 2 VDD_I C SDA ...
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... VDD_I VSS_I - - - (reserved) Figure 5: Pin Configuration (FS6054) 2 NAME DESCRIPTION Clock input for SDRAM clock outputs SCL Serial clock input SDA Serial data input/output SDRAM clock outputs (Byte 0) SDRAM clock outputs (Byte 1) SDRAM feedback clock outputs (Byte 2) OE ...
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April 1999 3.0 Programming Information Table 2: Clock Enable CONTROL INPUTS 3.1 Power-Up Initialization All outputs are enabled and active upon power-up, and all output control register bits are initialized to one. The outputs must be ...
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... Pin 26 Pin 26 Pin 23 Pin 23 Pin 22 Pin Pin 19 - Pin 18 OUTPUT PIN OUTPUT PIN OUTPUT PIN (FS6051) (FS6053) Pin 18 - Pin 11 Pin April 1999 (FS6054) Pin 11 Pin Pin 7 Pin 6 Pin 3 Pin 2 (FS6054) Pin 27 Pin 26 Pin 23 Pin Pin 19 Pin 18 (FS6054) Pin 17 Pin 4.5.99 ...
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April 1999 4.0 Dual Serial Interface Control This integrated circuit is a read/write slave device that supports both the Inter IC ...
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For an I C-bus interface, the device can support two de- vice addresses to permit multiple devices on one I The A2 address bit is ignored and can be set to either a one or a zero. 2 ...
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April 1999 Figure 6: Random Register Write Procedure (I S DEVICE ADDRESS W A REGISTER ADDRESS 7-bit Receive Register Address Device Address Acknowledge START WRITE Command Command From bus host to device Figure 7: Random Register Read Procedure (I ...
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SMBus: Block Write The Block Write command permits the SMBus master to write several bytes of data to sequential registers, starting by default at Register 0. The Block Write command, as noted in Figure 10, begins with the ...
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April 1999 5.0 Electrical Specifications Table 7: Absolute Maximum Ratings Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These conditions represent a stress rating only, and functional operation of the device at ...
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... Unless otherwise stated, all power supplies = 3.3V ± 5%, no load on any output, and ambient temperature range T characterization data and are not currently production tested to any specific limits. MIN and MAX characterization data are PARAMETER Overall (FS6050) Supply Current, Dynamic, with Loaded Outputs Supply Current, Static Serial Communication Inputs/Output (SDA, SCL) ...
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April 1999 Table 10: AC Timing Specifications Unless otherwise stated, all power supplies = 3.3V ± 5%, no load on any output, and ambient temperature range T characterization data and are not currently production tested to any specific limits. ...
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Table 11: Serial Interface Timing Specifications Unless otherwise stated, all power supplies = 3.3V ± 5%, no load on any output, and ambient temperature range T characterization data and are not currently production tested to any specific limits. MIN ...
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April 1999 Figure 14: SDRAM_0:17 Clock Output (3.3V Type 4 Clock Buffer) Low Drive Current (mA) Voltage (V) MIN. TYP. MAX 104 1 49 ...
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Package Information Table 12: 48-pin SSOP (7.5mm/0.300") Package Dimensions DIMENSIONS INCHES MILLIMETERS MIN. MAX. MIN. MAX. A 0.095 0.110 2.41 A 0.008 0.016 0.203 0.406 1 A 0.088 0.092 2. 0.008 0.0135 0.203 0.343 C 0.005 ...
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April 1999 Table 14: 28-pin SOIC (7.5mm/0.300") Package Dimensions DIMENSIONS INCHES MILLIMETERS MIN. MAX. MIN. MAX. A 0.093 0.104 2.35 A 0.004 0.012 0. 0.08 0.100 2. 0.013 0.013 0.33 C 0.009 0.009 0.23 D ...
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Table 16: 28-pin SSOP (5.3mm/0.209") Package Dimensions DIMENSIONS INCHES MILLIMETERS MIN. MAX. MIN. MAX. A 0.068 0.078 1.73 A 0.002 0.008 0. 0.066 0.07 1. 0.01 0.015 0.25 C 0.005 0.008 0.13 D 0.396 0.407 ...
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... FS6051 11257-806 11257-816 11257-803 FS6053 11257-813 11257-804 FS6054 11257-814 2 Purchase components of American Microsystems, Inc., or one of its sublicensed Associated Companies conveys a license under Philips the I C Standard Specification as defined by Philips. Copyright © 1998 American Microsystems, Inc. Devices sold by AMI are covered by the warranty and patent indemnification provisions appearing in its Terms of Sale only. AMI makes no warranty, express, statutory implied or by description, regarding the information set forth herein or regarding the freedom of the described devices from patent infringement ...
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... Reduction of EMI The primary concern when designing the board layout for this device is the reduction of electromagnetic interfer- ence (EMI) generated by the 18 copies of the 100MHz SDRAM clock assumed the reader is familiar with basic transmission line theory. 8.1.1 Layout Guidelines To obtain the best performance, noise should be mini- mized on the power and ground supplies to the IC ...
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... RC delay of the load capacitance and the line impedance. Also note that the output driver impedance will vary slightly with the output logic state (high or low). 8.2 Dynamic Power Dissipation High-speed clock drivers require careful attention to power dissipation. Transient power (P be derived from 2 ...