MBM29F040C Fujitsu Media Devices, MBM29F040C Datasheet - Page 15

• Manufacturer Part Number: MBM29F040C
• Description: 4M (512K X 8) BIT
• Manufacturer: Fujitsu Media Devices

Write Operation Status
Notes: 1. Performing successive read operations from any address will cause DQ
DQ
Data Polling
In Progress
Exceeded
Time Limits
The MBM29F040C device features Data Polling as a method to indicate to the host that the Embedded Algorithms
are in progress or completed. During the Embedded Program Algorithm an attempt to read the device will produce
the compliment of the data last written to DQ
to read the device will produce the true data last written to DQ
attempt to read the device will produce a “0” at the DQ
an attempt to read the device will produce a “1” at the DQ
in Figure 15.
For chip erase, and sector erase the Data Polling is valid after the rising edge of the sixth WE pulse in the six
write pulse sequence. For sector erase, the Data Polling is valid after the last rising edge of the sector erase
WE pulse. Data Polling must be performed at sector address within any of the sectors being erased and not a
protected sector. Otherwise, the status may not be valid. Once the Embedded Algorithm operation is close to
being completed, the MBM29F040C data pins (DQ
is asserted low. This means that the device is driving status information on DQ
that byte’s valid data at the next instant of time. Depending on when the system samples the DQ
read the status or valid data. Even if the device has completed the Embedded Algorithm operation and DQ
a valid data, the data outputs on DQ
the successive read attempts.
The Data Polling feature is only active during the Embedded Programming Algorithm, Embedded Erase
Algorithm, or sector erase time-out. (See Table 6.)
See Figure 9 for the Data Polling timing specifications and diagrams.
7
2. Reading the byte address being programmed while in the erase-suspend program mode will indicate logic
3. DQ
“1” at the DQ
0
Embedded Program Algorithm
Embedded Erase Algorithm
Erase
Suspended
Mode
Embedded Program Algorithm
Program/Erase in Embedded Erase Algorithm
Erase
Suspended
Mode
and DQ
1
2
are reserve pins for future use. DQ
bit. However, successive reads from the erase-suspended sector will cause DQ
Erase Suspend Read
(Erase Suspended Sector)
Erase Suspend Read
(Non-Erase Suspended Sector)
Erase Suspend Program
Non-Erase Suspended Sector)
Erase Suspend Program
(Non-Erase Suspended Sector)
Status
Table 6
0
to DQ
7
6
. Upon completion of the Embedded Program Algorithm, an attempt
Hardware Sequence Flags
may be still invalid. The valid data on DQ
7
) may change asynchronously while the output enable (OE)
7
output. Upon completion of the Embedded Erase Algorithm
4
7
is for Fujitsu internal use only.
output. The flowchart for Data Polling (DQ
7
. During the Embedded Erase Algorithm, an
MBM29F040C
Data
DQ
DQ
DQ
DQ
DQ
0
1
0
7
7
7
7
7
(Note 1)
Toggle
Toggle
Toggle
Toggle
Toggle
Toggle
Data
DQ
1
6
7
6
at one instant of time and then
to toggle.
Data
DQ
0
0
0
0
1
1
1
0
5
to DQ
7
Data
DQ
will be read on
7
-55/-70/-90
0
1
0
0
0
1
0
output, it may
3
7
2
) is shown
to toggle.
(Note 2)
Toggle
Toggle
Data
DQ
N/A
N/A
7
1
1
1
has
2
15