MBM29PL65LM Fujitsu Media Devices, MBM29PL65LM Datasheet - Page 6

• Manufacturer Part Number: MBM29PL65LM
• Description: FLASH MEMORY CMOS 64 M (4M X 16) BIT MirrorFlashTM
• Manufacturer: Fujitsu Media Devices

6
MBM29PL65LM
*1 : The command combinations not described in “MBM29PL65LM Standard Command Definitions” are
*2 : Both of these reset commands are equivalent except for "Write to Buffer Abort" reset.
*3 : The Erase Suspend and Erase Resume command are valid only during a sector erase operation.
*4 : The Set to Fast Mode command is required prior to the Fast Program command.
*5 : The Reset from Fast Mode command is required to return to the read mode when the device is in fast
Reset*
Reset*
Autoselect
Program
Chip Erase
Sector Erase
Program/Erase Suspend*
Program/Erase Resume*
Set to Fast Mode*
Fast Program*
Reset from Fast Mode*
Write to Buffer
Program Buffer to Flash
(Confirm)
Write to Buffer Abort Reset*
Extended Sector Group
Protection*
Query*
HiddenROM Entry*
HiddenROM Program *
HiddenROM Exit*
RA
PA
SA
SGA
RD
PD
WBL
HRA
illegal.
mode.
2
2
9
Command
Sequence
7,
Address of the memory location to be read.
Address of the memory location to be programmed Addresses are latched on the falling edge of the
write pulse.
Address of the sector to be erased. The combination of A
will uniquely select any sector. See “Sector Address Table”
Sector Group Address to be protected. See “Sector Group Address Table”. Specify SGA which
constitutes from A
Data read from location RA during read operation.
Data to be programmed at location PA. Data is latched on the rising edge of write pulse.
Write Buffer Location
Address of the HiddenROM area ; 000000h to 00007Fh
*
8
4
11
4
10
5
10,
3
*
3
11
MBM29PL65LM Standard Command Definitions Table*
6
21
to A
Cycles
-90/10
Req'd
Write
Bus
20
17
1
3
3
4
6
6
1
1
3
2
2
1
3
4
1
3
4
4
and (A
XXXh F0h
XXXh B0h
XXXh 30h
XXXh A0h
XXXh 90h XXXh 00h
XXXh 60h
Addr Data Addr
555h
555h
555h
555h
555h
555h
555h
555h
555h
555h
555h
First Bus
55h
SA
Cycle
Write
6
, A
AAh 2AAh
AAh 2AAh
AAh 2AAh
AAh 2AAh
AAh 2AAh
AAh 2AAh
AAh 2AAh
AAh 2AAh
AAh 2AAh
AAh 2AAh
AAh 2AAh
29h
98h
3
, A
2
Second Bus
, A
SGA
PA
—
—
—
—
—
1
Cycle
Write
, A
0
Data
55h
55h
55h
55h
55h
55h
55h
55h
60h
55h
55h
55h
) = (0, 0, 0, 1, 0).
PD
—
—
—
—
—
*
12
Third Bus
Addr Data
555h
555h
555h
555h
555h
555h
555h
SGA
555h
555h
555h
SA
—
—
—
—
—
—
—
Cycle
Write
21
, A
F0h
90h
A0h
80h
80h
20h
25h
F0h
40h
88h
A0h
90h
—
—
—
—
—
—
—
20
, A
SGA
19
00h
RA
XXXh
Addr
555h
555h
Fourth Bus
Read/Write
, A
PA
SA
PA
—
—
—
—
—
—
—
—
—
—
*
*
Cycle
*
13
13
18
13
, A
1
04h
RD
SD
Data
17
AAh
AAh
0Fh
00h
PD
PD
—
—
—
—
—
—
—
—
—
—
, A
*
*
*
13
13
13
16
2AAh 55h 555h 10h
2AAh 55h
Addr Data Addr Data
Fifth Bus
and A
PA
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Cycle
Write
15
PD
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Sixth Bus
WBL
SA
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Cycle
Write
30h
PD
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—