fs7140 ON Semiconductor, fs7140 Datasheet - Page 12

• Manufacturer Part Number: fs7140
• Description: Programmable Phase- Locked Loop Clock Generator
• Manufacturer: ON Semiconductor

Table 8. FS7145 REGISTER MAP
Address
Byte 7
Byte 6
Byte 5
Byte 4
Byte 3
Byte 2
Byte 1
Byte 0
Modulus = N + 1 (N = 0 to 11); See Table 12
Must be set
Must be set
Must be set
FBKDIV[7]
REFDIV[7]
1 = CMOS
Reserved
Reserved
Reserved
0 = PECL
POST2[3]
POST3[1]
(Bit 63)
(Bit 55)
(Bit 47)
(Bit 39)
(Bit 31)
(Bit 23)
(Bit 15)
CMOS
Modulus = 1, 2, 4 or 8;
(Bit 7)
BIT 7
to “0”
to “0”
to “0”
128
128
See Table 12
divider output
Must be set
Must be set
FBKDSRC
FBKDIV[6]
REFDIV[6]
cap select
POST2[2]
POST3[0]
Reserved
Reserved
Loop filter
0 = VCO
1 = Post
(Bit 62)
(Bit 54)
(Bit 46)
(Bit 38)
(Bit 30)
(Bit 22)
(Bit 14)
output
(Bit 6)
BIT 6
to “0”
to “0”
LC
64
64
See the Feedback Divider section for disallowed FBKDIV values
1 = Powered
1 = Powered
FBKDIV[13]
Must be set
0 = Normal
0 = Normal
FBKDIV[5]
REFDIV[5]
POST2[1]
Reserved
Loop filter resistor select
(Bit 61)
SHUT2
(Bit 53)
(Bit 45)
(Bit 37)
(Bit 29)
(Bit 21)
SHUT1
(Bit 13)
(Bit 5)
BIT 5
to “0”
down
LR[1]
down
8192
32
32
http://onsemi.com
See the Feedback Divider section for disallowed FBKDIV values
FBKDIV[12]
1 = REF pin
Must be set
Must be set
REFDSRC
0 = Crystal
REFDIV[4]
FBKDIV[4]
POST2[0]
Reserved
Reserved
oscillator
(Bit 60)
(Bit 52)
(Bit 44)
(Bit 36)
(Bit 28)
(Bit 20)
(Bit 12)
(Bit 4)
BIT 4
to “0”
to “0”
LR[0]
4096
16
16
12
FBKDIV[11]
REFDIV[11]
Must be set
Must be set
Must be set
REFDIV[3]
FBKDIV[3]
Reserved
Reserved
Reserved
POST1[3]
(Bit 59)
(Bit 51)
(Bit 43)
(Bit 35)
(Bit 27)
(Bit 19)
(Bit 11)
(Bit 3)
BIT 3
to “0”
to “0”
to “0”
2048
2048
8
8
Modulus = N + 1 (N = 0 to 11); See Table 12
REFDIV[10]
Must be set
Must be set
Must be set
FBKDIV[10]
FBKDIV[2]
REFDIV[2]
Reserved
Reserved
Reserved
POST1[2]
(Bit 58)
(Bit 50)
(Bit 42)
(Bit 34)
(Bit 26)
(Bit 18)
(Bit 10)
(Bit 2)
BIT 2
to “0”
to “0”
to “0”
1024
1024
4
4
“0” = negative
“1” = positive
Charge pump current select
Must be set
SYNCPOL
FBKDIV[9]
FBKDIV[1]
REFDIV[9]
REFDIV[1]
POST1[1]
Reserved
(Bit 57)
(Bit 49)
(Bit 41)
(Bit 33)
(Bit 25)
(Bit 17)
(Bit 9)
(Bit 1)
BIT 1
CP[1]
to “0”
512
512
2
2
“0” = negative
“1” = positive
Must be set
REFDIV[8]
REFDIV[0]
FBKDIV[8]
FBKDIV[0]
POST1[0]
Reserved
SYNCEN
(Bit 56)
(Bit 48)
(Bit 40)
(Bit 32)
(Bit 24)
(Bit 16)
(Bit 8)
(Bit 0)
BIT 0
CP[0]
to “0”
256
256
1
1