stv8226t STMicroelectronics, stv8226t Datasheet - Page 28

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stv8226t

Manufacturer Part Number
stv8226t
Description
Multistandard Tv Audio Processor And Digital Sound Demodulator
Manufacturer
STMicroelectronics
Datasheet
I²S Interface
6
28/97
I²S Interface
A digital stereo input is available for a virtual Dolby source from an external decoder.
A digital stereo output (I²S compatible) is available for routing the demodulated signal or a converted
input audio signal into a Dolby Pro Logic Decoder or an external DAC. The STV82x6 I²S interface
drives the serial bus (SCK, WS, SDO) in Master mode in format 32.fs with a sampling frequency (f
of 32 kHz. An additional master clock (MCK) in format 256.fs (f
required for the slave interface.
Both Philips and Sony modes are supported with programmable Word Selection (WS) polarity
(register I2S). By default, all I²S digital outputs are set in high impedance and must be switched to
low impedance via register
A clock system output (SYSCK) is also available for clock peripherals using the same quartz
frequency as the STV82x6. By default, this clock output (identical to the crystal oscillator) is set to
high impedance and must be switched to low impedance via register
CTRL
before use.
S
= 8.192 MHz) is provided if
CTRL
before use.
STV82x6
S
)

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