cy2pp326 Cypress Semiconductor Corporation., cy2pp326 Datasheet

cy2pp326

Manufacturer Part Number

cy2pp326

Description

2 X 2 Clock And Data Switch Buffer

Manufacturer

Cypress Semiconductor Corporation.

Datasheet

1.CY2PP326.pdf (9 pages)

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Cypress Semiconductor Corporation

Document #: 38-07506 Rev.*D

Features

• Six ECL/PECL differential outputs

• Two ECL/PECL differential inputs

• Hot-swappable/-insertable

• 50 ps output-to-output skew

• 250 ps device-to-device skew

• 950 ps propagation delay (typical)

• 1.2 GHz Operation

• 2.8 ps RMS period jitter (max.)

• PECL mode supply range: V

• ECL mode supply range: V

• Industrial temperature range: –40°C to 85°C

• 32-pin 1.4mm TQFP package

• Temperature compensation like 100K ECL

• Pin Compatible with MC100ES6254

CLK0#

CLK1#

O EA#

O EB#

CLK0

CLK1

SEL0

SEL1

with V

Block Diagram

VCC

VEE

VCC

VEE

= 0V

Sync

= 2.5V± 5% to 3.3V±5%

= –2.5V± 5% to –3.3V±5%

•

Bank A

B ank B

3901 North First Street

2 x 2 Clock and Data Switch Buffer

Functional Description

The CY2PP326 is a low-skew, low propagation delay 2 x 2

differential clock, data switch, and fanout buffer targeted to

meet the requirements of high-performance clock and data

distribution applications. The device is implemented on SiGe

technology and has a fully differential internal architecture that

is optimized to achieve low-signal skews at operating

frequencies of up to 1.5 GHz.

The device features two differential input paths which are mul-

tiplexed internally to six outputs grouped in two banks. The

muxes are controlled by SEL(0:1) control inputs. The

CY2PP326 may function as 1:6 or 2x 1:3 clock/data buffer and

as a clock/data repeater or multiplexer.

Since the CY2PP326 introduces negligible jitter to the timing

budget, it is the ideal choice for distributing high frequency,

high precision clocks across back-planes and boards in

communication systems and for switching data signals

between different channels. Furthermore, advanced circuit

design schemes, such as internal temperature compensation,

ensure that the CY2PP326 delivers consistent, guaranteed

performance over differing platforms.

QA0

QA0#

QA1

QA1#

QA2

QA2#

Q B0

Q B0#

Q B1

Q B1#

Q B2

Q B2#

•

Pin Configuration

CLK1#

OEB#

CLK1

San Jose

SEL1

VCC

VEE

CA 95134

CY2PP326

FastEdge™ Series

Revised July 28, 2004

•

CY2PP326

408-943-2600

VCC

VEE

OEA#

CLK0

CLK0#

SEL0

VEE

VCC

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