cy2vc521-2 Cypress Semiconductor Corporation., cy2vc521-2 Datasheet
cy2vc521-2
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cy2vc521-2 Summary of contents
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... The CY2VC521 PLL-based clock generator with VCXO control and very low output jitter. When the user connects a fundamental mode 27 MHz crystal, this device generates a 216 MHz output clock. The CY2VC521-2 has one LVDS output pair tuned to drive two standard LVDS loads and operates from a single 3.3V power supply. ...
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... VCXO Control Voltage: VIN has a positive control slope, meaning that increasing the voltage on VIN causes the output frequency to increase. The nominal output frequency is determined when VIN = 1.65V Differential output clock Select: Hold this pin LOW for normal operation No Connect: NC pins are not connected to the die 3.3V power supply Ground CY2VC521-2 Page [+] Feedback ...
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... Document Number: 001-15599 Rev. *E PLL Multiplier Value 8 Crystal Input Interface The CY2VC521-2 is designed for use with parallel resonant crystal. This assumes board capacitance on each crystal signal traces, plus 26 pF internally on both the XIN and XOUT pins. The crystal is required to meet the parameters shown in “ ...
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... Description (min). (Ensure power ramp is monotonic.) DD Description Condition Outputs on and terminated SEL = V DD SEL = V SS ≤ VIN ≤ ≤ VIN ≤ CY2VC521-2 Min Max Unit –0.5 4.4 V –0 °C –65 150 °C – 135 2000 – ...
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... MHz carrier 1 MHz offset from 216 MHz carrier 10 MHz offset from 216 MHz carrier Measured at zero crossing point Time for CLK to reach valid frequency measured from the time Figure 2 on page 3. CY2VC521-2 Min Typ Max – 216 – ±115 – – ...
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... Figure 4. Output Voltage Swing V V OD1 OD2 Δ OD1 OD2 Figure 5. Output Offset Voltage CLK 25Ω V 25Ω CLK# Figure 6. Output Rise and Fall Time CLK# 80% 80% 20% CLK PERIOD CY2VC521 PERIOD Page [+] Feedback ...
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... Part Number Pb-Free CY2VC521ZXC-2 16-Pin TSSOP CY2VC521ZXC-2T 16-Pin TSSOP - Tape and Reel Package Drawings and Dimensions Document Number: 001-15599 Rev. *E Package Description Figure 8. 16-Pin TSSOP 4.40 MM Body CY2VC521-2 Product Flow Commercial, 0° to 70°C Commercial, 0° to 70°C 51-85091 *B Page [+] Feedback ...
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... Document History Page Document Title: CY2VC521-2 Low Noise LVDS Clock Generator with VCXO Document Number: 001-15599 Submission REV. ECN NO. Date ** 1285703 See ECN *A 2669117 3/5/2009 KVM/AESA Removed MSL spec *B 2697706 04/20/2009 KVM/PYRS Added VCXO Control Curve figure and text *C 2705609 05/15/2009 ...
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... Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement. Document Number: 001-15599 Rev. *E All products and company names mentioned in this document may be the trademarks of their respective holders. cypress.com/go/plc Revised May 14, 2010 CY2VC521-2 PSoC Solutions psoc.cypress.com/solutions PSoC 1 | PSoC 3 ...