cy2v9950 Cypress Semiconductor Corporation., cy2v9950 Datasheet - Page 2

• Manufacturer Part Number: cy2v9950
• Description: 200-mhz Multi-output Zero Delay Buffer
• Manufacturer: Cypress Semiconductor Corporation.

Document #: 38-07436 Rev. *A
Pin Definitions
Device Configuration
The outputs of the CY2V9950 can be configured to run at
frequencies ranging from 6 to 200 MHz. Banks 3 and 4 output
dividers are controlled by 3F[1:0] and 4F[1:0] as indicated in
Table 1 and 2 respectively.
Table 1. Output Divider Settings – Bank 3
Table 2. Output Divider Settings – Bank 4
Notes:
29
13
27
22
4
24, 23, 26,
25, 1, 32, 3, 2
31
19, 20, 15,
16,10,11, 6,
7
21
12
5
14,30
8, 9, 17, 18,
28
1.
2.
3.
4.
5.
6.
‘PD’ indicates an internal pull-down and ‘PU’ indicates an internal pull-up. ‘3’ indicates a three-level input buffer.
A bypass capacitor (0.1µF) should be placed as close as possible to each positive power pin (<0.2”). If these bypass capacitors are not close to the pins their
high frequency filtering characteristic will be cancelled by the lead inductance of the traces.
When TEST = MID and sOE# = HIGH, PLL remains active with nF[1:0] = LL functioning as an output disable control for individual output banks. The 1F[0:1]
and 2F[0:1] pins should be either tied to mid-level or left floating (on-chip resistors will bias to mid-level) during normal operation.
LL disables outputs if TEST = MID and sOE# = HIGH.
When 4Q[0:1] are set to run inverted (HH mode), sOE# disables these outputs HIGH when PE = HIGH, sOE# disables them LOW when PE = LOW.
These outputs are undivided copies of the VCO clock. Therefore, the formulas in this column can be used to calculate the VCO operating frequency at a given
reference frequency (F
frequency that is within the range specified by FS pin. Refer to Table 4.
Pin
3F[1:0]
4F[1:0]
Other
Other
LL
LL
HH
HH
[4]
[4]
REF
FB
TEST
sOE#
PE
nF[1:0]
FS
nQ[1:0]
VDDQ1
VDDQ3
VDDQ4
VDD
VSS
Name
[2]
REF
[2]
[2]
[2]
) and divider and feedback configurations. The user must select a configuration and a reference frequency that will generate a VCO
I, PD
I, PU
PWR
PWR
PWR
PWR
PWR
I/O
K – Bank3 Output Divider
M – Bank4 Output Divider
O
I
I
I
I
I
[1]
LVTTL/LVCMOS
LVTTL
3-Level
2-Level
LVTTL
3-Level
3-Level
LVTTL
Power
Power
Power
Power
Power
Inverted
Type
2
4
1
2
1
[5]
Reference Clock Input.
Feedback Input.
When MID or HIGH, disables PLL (except for conditions of note 3).
REF goes to all outputs. Set LOW for normal operation.
Synchronous Output Enable. When HIGH, it stops clock outputs (except
2Q0 and 2Q1) in a LOW state (for PE = H or M) – 2Q0 and 2Q1 may be
used as the feedback signal to maintain phase lock. When TEST is held at
MID level and sOE# is high, the nF[1:0] pins act as output disable controls
for individual banks when nF[1:0] = LL. Set sOE# LOW for normal
operation.
Selects Positive or Negative Edge Control and High or Low output
drive strength. When LOW / HIGH the outputs are synchronized with the
negative/positive edge of the reference clock. Please see Table 5.
Select frequency of the outputs. Please see Tables 1 and 2.
Selects VCO operating frequency range. Please see Table 4.
Four banks of two outputs. Please see Tables 1 and 2 for frequency
settings.
Power supply for Bank 1 and Bank 2 output buffers. Please see Table 6
for supply level constraints
Power supply for Bank 3 output buffers. Please see Table 6 for supply
level constraints
Power supply for Bank 4 output buffers. Please see Table 6 for supply
level constraints
Power supply for internal circuitry. Please see Table 6 for supply level
constraints
Ground.
The divider settings, output frequencies, and possible config-
urations of connecting FB to ANY output are summarized in
Table 3.
Table 3. Output Frequency Settings
The 3-level FS control pin setting determines the nominal
operating frequency range of the divide-by-one outputs of the
device. The CY2V9950 PLL operating frequency range that
corresponds to each FS level is given in Table 4.
Configuration
1Qn, 2Qn
FB to
3Qn
4Qn
Description
1Q, 2Q
M x F
K x F
F
REF
REF
REF
[6]
Output Frequency
(M/K) x F
(1/K) x F
F
3Q
REF
REF
REF
CY2V9950
(K/M) x F
(1/M) x F
Page 2 of 9
F
4Q
REF
REF
REF
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