cy2048waf Cypress Semiconductor Corporation., cy2048waf Datasheet

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cy2048waf

Manufacturer Part Number
cy2048waf
Description
Flash Programmable Capacitor Tuning Array Die For Crystal Oscillator Xo
Manufacturer
Cypress Semiconductor Corporation.
Datasheet
Cypress Semiconductor Corporation
Document #: 38-07738 Rev. *A
Features
• Flash-programmable capacitor tuning array for low
• Low clock output jitter
• Flash-programmable dividers
• Two-pin programming interface
• On-chip oscillator runs from 10–48-MHz crystal
• Five selectable post-divide options, using reference
• Programmable asynchronous or synchronous OE and
• 2.7V to 3.6V operation
• Controlled rise and fall times and output slew rate
Block Diagram
Die Pad Description
ppm initial frequency clock output
— 4 ps typ. RMS period jitter
— ±30 ps typ. peak-to-peak period jitter
oscillator output
PWR_DWN modes
2
1
3
4
X IN
X O U T
P D # /O E
V D D
H o riz o n ta l S c rib e
Y (m a x )
X (m a x )
7 C 8 0 3 3 0 A
(SDATA/VPP)
PD#/OE
Flash Programmable Capacitor Tuning Array Die
XOUT
O U T
V S S
XIN
6
5
d ie # /re v
V e rtic a l
S c rib e
OSCILLATOR
CRYSTAL
3901 North First Street
Pad pitch: 175 µm (min.)
Notes
X(max): 980 µm, Y(max): 988 µm
Scribe: X = 70 µm, Y = 86 µm
Bond pad opening: 85 µm x 85 µm
Wafer thickness: 11 mils (Typ.)
VDD
Benefits
/ 1, 2, 4, 8, 16
• Enables fine-tuning of output clock frequency by
• Allows multiple programming opportunities to correct
• Enables programming of output frequency after
• PPM clock output error can be adjusted in package
• Provides flexibility in output configurations and testing
• Enables low-power operation or output enable function
• Provides flexibility for system applications through
• Enables encapsulation in small-size, surface-mount
:
adjusting C
errors, and control excess inventory
packaging
selectable instantaneous or synchronous change in
outputs
packages
VSS
for Crystal Oscillator(XO)
San Jose
Load
CONFIGURATION
of the crystal
,
CA 95134
Revised December 12, 2005
OUT
(SCL)
CY2048WAF
408-943-2600
[+] Feedback

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cy2048waf Summary of contents

Page 1

... V e rtic rib e Bond pad opening: 85 µ µm Pad pitch: 175 µm (min.) Wafer thickness: 11 mils (Typ /re v • 3901 North First Street • San Jose CY2048WAF of the crystal OUT (SCL 95134 • 408-943-2600 Revised December 12, 2005 [+] Feedback ...

Page 2

... Serial data pin used for programming in test mode OUT 6 Clock output SCL Serial clock for programming in test mode VSS 5 Ground Document #: 38-07738 Rev. *A Description X coordinate (µm) –360.8 –360.8 –360.8 –360.8 CY2048WAF Y coordinate (µm) 353.7 134.1 –42.6 –275.9 360.0 353.7 360.0 –354.5 Page [+] Feedback ...

Page 3

... Input = V DD Output = V SS Output = Load 3.3V, 48 MHz DD PD > 0.5V 500 IN DD PD#/OE pin XIN = 0 300 CY2048WAF Min. Typ. Max. Unit 10 – 48 MHz Ω – – 40 values are 4.5 – – – – – – – fF Min. Typ. ...

Page 4

... XIN XOUT Figure 1. Programmable Load Capacitance CY2048WAF Min. Typ. Max. Unit 0.625 – 48 MHz 2 – – ...

Page 5

... Weakly pulled LOW T STP Figure 2. Power-down Timing Weakly pulled LOW T T PZX PXZ Weakly pulled LOW T T PXZ PZX Figure 3. Output Enable Timing T S Figure 4. VDD Power-up Timing CY2048WAF Min. Max. Unit 1.5T + 350 ns out 350 1.5T + 350 ns out 350 ns 1.5T + 350 ...

Page 6

... Cypress against all charges. DUT GND 50 Figure 5. Duty Cycle Definition 80 20 Figure 6. Package Type Wafer CY2048WAF Output C LOAD Operating Range (TJ) Industrial,–40 °C to 125°C Page [+] Feedback ...

Page 7

... Document History Page Document Title: CY2048WAF Flash Programmable Capacitor Tuning Array Die for Crystal Oscillator(XO) Document Number: 38-07738 Orig. of REV. ECN NO. Issue Date Change ** 319840 See ECN RGL *A 413511 See ECN RGL Document #: 38-07738 Rev. *A Description of Change New data sheet Minor Change: Pls. post in the web ...

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