cy26126 Cypress Semiconductor Corporation., cy26126 Datasheet
cy26126
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cy26126 Summary of contents
Page 1
... Meets critical timing requirements in complex system designs Input Frequency Range 25 MHz P Comp OSC. Q VCO P PLL VSS VDD • 3901 North First Street CY26126 Dual Output 125-MHz Clock Generator Benefits Output Frequencies 2 copies of 125 MHz (3.3V) OUTPUT MULTIPLEXER 125 MHz AND DIVIDERS 125 MHz • ...
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... SS V – 0 Min. 3.14 0 0.05 Conditions – CMOS Levels 70 CMOS Levels 30 Sum of Core and Output Current CY26126 Max. Unit. 7.0 125 125 0.3 DD Typ. Max. Unit 3.3 3.47 70 ° 150 mW 25 MHz 500 ms Min. ...
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... Output Clock Fall Time, 80 Peak to Peak period jitter OUTPUTS GND t1 t2 50% Figure 1. Duty Cycle Definition t2/ 80% CLK 20% Figure 2. Rise and Fall Time Definitions Package Type Operating Range 8-Pin SOIC Commercial CY26126 Min. Typ. Max 0.8 1.4 DD 0.8 1.4 DD 200 3 CLK out C ...
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... The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. Advance Information 8-Lead (150-Mil) SOIC S8 CY26126 51-85066-A Page ...
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... Document Title: CY26126 Dual Output 125-MHz Clock Generator Document Number: 38-07351 Issue REV. ECN NO. Date ** 112233 03/01/02 *A 121891 12/14/02 Document #: 38-07351 Rev. *A Advance Information Orig. of Change CKN New data sheet RBI Power up requirements added to Operating Conditions Information CY26126 Description of Change Page ...