cy2xl11 Cypress Semiconductor Corporation., cy2xl11 Datasheet

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cy2xl11

Manufacturer Part Number
cy2xl11
Description
100 Mhz Lvds Clock Generator
Manufacturer
Cypress Semiconductor Corporation.
Datasheet

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Part Number:
cy2xl11ZXC
Manufacturer:
Cypress
Quantity:
162
Features
Table 1. Pin Definition - 8-Pin TSSOP
Cypress Semiconductor Corporation
Document Number: 001-42886 Rev. *C
Pinouts
Pin Number
One LVDS Output Pair
Output Frequency: 100 MHz
External Crystal Frequency: 25 MHz
Low RMS Phase Jitter at 100 MHz, using 25 MHz Crystal
(637 kHz to 10 MHz): 0.53 ps (Typical)
Pb-free 8-Pin TSSOP Package
Supply Voltage: 3.3V or 2.5V
Commercial Temperature Range
Logic Block Diagram
1, 8
3, 4
6,7
2
5
External
Crystal
CLK#, CLK
XOUT, XIN
Pin Name
VDD
VSS
OE
OE
XOUT
XIN
XTAL output and input
XOUT
LVDS output
CMOS input
VDD
VSS
XIN
OSCILLATOR
I/O Type
Power
Power
CRYSTAL
Figure 1. Pin Diagram - 8-Pin TSSOP
198 Champion Court
1
2
3
4
3.3V or 2.5V power supply. All supply current flows through pin 1
Ground
Parallel resonant crystal interface
Output Enable. When HIGH, the output is enabled. When LOW, the
output is high impedance
Differential clock output
100 MHz LVDS Clock Generator
LOW-NOISE
Functional Description
The CY2XL11 is a PLL (Phase Locked Loop) based high
performance clock generator with a crystal oscillator interface
and one LVDS output pair. It is optimized to generate PCI
Express, FC, and other high performance clock frequencies. It
also produces an output frequency that is four times the crystal
frequency. It uses Cypress’s low noise VCO technology to
achieve less than 1 ps typical RMS phase jitter, that meets high
performance systems’ jitter requirements.
PLL
8
7
6
5
San Jose
VDD
CLK
CLK#
OE
,
OUTPUT
DIVIDER
Description
CA 95134-1709
Revised June 12, 2009
CY2XL11
408-943-2600
CLK
CLK#
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cy2xl11 Summary of contents

Page 1

... Document Number: 001-42886 Rev. *C 100 MHz LVDS Clock Generator Functional Description The CY2XL11 is a PLL (Phase Locked Loop) based high performance clock generator with a crystal oscillator interface and one LVDS output pair optimized to generate PCI Express, FC, and other high performance clock frequencies. It also produces an output frequency that is four times the crystal frequency. It uses Cypress’ ...

Page 2

... CLK and CLK 3.3V or 2.5V 100Ω DD TERM between CLK and CLK 3.3V or 2.5V 100Ω DD TERM between CLK and CLK# Three-state output, PD#/ Figure 8 on page 5. CY2XL11 Output Frequency (MHz) 100 Min Max Unit –0.5 4.4 V –0 0 –65 150 °C 135 ° ...

Page 3

... Time from falling edge stopped outputs (Asynchronous) Time from rising edge outputs at a valid frequency (Asynchronous) Time for CLK to reach valid frequency measured from the time (min Description CY2XL11 Min Typ Max Unit 0.7*V – – – – 0.3*V ...

Page 4

... CLK# Figure 4. Output Rise or Fall Time CLK# 80% 80% 20% CLK Figure 5. Duty Cycle Timing PERIOD Figure 6. Output Enable and Disable Timing OHZ OE High Impedance CY2XL11 V OD2 OD2 PERIOD Page [+] Feedback ...

Page 5

... Noise Power Termination Circuits Document Number: 001-42886 Rev. *C Figure 7. RMS Phase Jitter Phase noise Phase noise mark Offset Frequency f2 f1 Area Under the Masked Phase Noise Plot RMS Jitter = Figure 8. LVDS Termination CLK 100Ω CLK# CY2XL11 Page [+] Feedback ...

Page 6

... Package Description PIN 1 ID DIMENSIONS IN MM[INCHES] MIN. 0.25[0.010] 1.10[0.043] MAX. BSC GAUGE 0°-8° PLANE 0.076[0.003] SEATING PLANE CY2XL11 Product Flow Commercial, –5°C to 70°C Commercial, –5°C to 70°C MAX. 0.50[0.020] 0.09[[0.003] 0.70[0.027] 0.20[0.008] 51-85093-*A Page [+] Feedback ...

Page 7

... Document History Page Document Title: CY2XL11 100 MHz LVDS Clock Generator Document Number: 001- 42886 ECN NO. Submission Orig. of REV. Date Change ** 2117527 See ECN WWZ/KVM *A 2669117 03/05/2009 *B 2700242 04/30/2009 *C 2718433 06/12/2009 WWZ/HMT No change. Submit to ECN for product launch. Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’ ...

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