cy2dl818 Cypress Semiconductor Corporation., cy2dl818 Datasheet

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cy2dl818

Manufacturer Part Number
cy2dl818
Description
1 8 Clock Fanout Buffer
Manufacturer
Cypress Semiconductor Corporation.
Datasheet

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Part Number:
cy2dl818ZI
Manufacturer:
SKYWORKS
Quantity:
36
Cypress Semiconductor Corporation
Document #: 38-07058 Rev. *B
Features
Block Diagram
• Low voltage operation
• V
• 1:8 fanout
• Single-input-configurable for LVDS, LVPECL, or LVTTL
• 8 pair of LVDS Outputs
• Drives either a 50-ohm or 100-ohm load (selectable)
• Low input capacitance
• Low output skew
• Low propagation delay
• Typical (tpd < 4 ns)
• Packages available include: TSSOP
• Does not exceed Bellcore 802.3 standards
• Operation at => 350 MHz – 700 Mbps
INPUT A
INPUT B
InConfig
DD
(LVPECL / LVDS / LVTTL)
= 3.3V
CNTRL
INPUT
10
11
6
7
OUTPUT
33
32
28
27
31
30
22
21
37
36
35
34
26
25
24
23
(LVDS)
3901 North First Street
Q5A
Q3A
Q3B
Q4A
Q4B
Q5B
Q6A
Q6B
Q7A
Q7B
Q8A
Q8B
Q1A
Q1B
Q2A
Q2B
Description
This Cypress series of network circuits is produced using
advanced 0.35-micron CMOS technology, achieving the
industry’s fastest logic.
The Cypress CY2DL818 fanout buffer features a single LVDS
or a single-ended LVTTL-compatible input and eight LVDS
output pairs.
Designed for data communications clock management appli-
cations, the large fanout from a single input reduces loading
on the input clock. The Cypress CY2DL818 is ideal for both
level translations from single-ended to LVDS and/or for the
distribution of LVDS-based clock signals.
The Cypress CY2DL818 has configurable input and output
functions. The input can be selectable for LVCMOS/LVTTL,
LVPECL, or LVDS signals, while the output drivers support
standard and high-drive LVDS. Drive either a 50-ohm or
100-ohm line with a single part number/device.
Pin Configuration
San Jose
1:8 Clock Fanout Buffer
INPUT A
INPUT B
InConfig
CNTRL
GND
GND
GND
VDD
GND
GND
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
38 pin TSSOP
CA 95134
Revised December 15, 2002
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
Q3B
Q8A
GND
Q1A
Q1B
Q2A
Q2B
Q3A
Q4A
Q4B
VDD
Q5A
Q6A
Q6B
Q7A
Q7B
Q8B
GND
Q5B
CY2DL818
408-943-2600
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cy2dl818 Summary of contents

Page 1

... Designed for data communications clock management appli- cations, the large fanout from a single input reduces loading on the input clock. The Cypress CY2DL818 is ideal for both level translations from single-ended to LVDS and/or for the distribution of LVDS-based clock signals. The Cypress CY2DL818 has configurable input and output functions ...

Page 2

... Input – Bar Input Input – Bar Test Conditions = Max DD Input toggling 50% Duty Cycle, Outputs Open V = Max DD Input toggling 50% Duty Cycle, Outputs Open fL = 100 MHz CY2DL818 Pin Description (logic = 0) (logic = 1) “default pull-up” Output Voltage Value V Voutput 1 ...

Page 3

... IL CL – and and C intrinsic external See Figure 3 CL – and and C intrinsic external See Figure OUT OUT CY2DL818 + 0. 0. 0.9V DD Min. Typ. Max. Unit 100 600 mV IV I/2 2.4 – ( ± ...

Page 4

... Standard Load Circuit. LVDS V = 100 mV ID Idd @ 25°C Idd (mA) vs. Input Freq. (MHz) High or B Drive Curves Standard Drive Curves 140 240 340 Input Freq. (MHz) LD 3.3 LD 3.465 HD 3.135 HD 3.3 CY2DL818 Min. Typ Max Unit 4.5 ns 4.5 ns 200 ps 200 ps 1.6 ns Min. Typ ...

Page 5

... V0Y - V0Z 20 ns; pulse rate = 50 Mpps; pulse width = 10 0.2 ns. CY2DL818 TPA 50 TPC 50 TPB [3,4,5, ...

Page 6

... & fig CY2DL818 TPA 50 TPC 50 TPB 100% 80% 20 [3,4,5,6] [8] [9] ’ ...

Page 7

... Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. Package Type 38-pin TSSOP 38-pin TSSOP–Tape and Reel 38-pin TSSOP 38-pin TSSOP–Tape and Reel 38-pin TSSOP (4.40 mm body) Z38 CY2DL818 Product Flow Industrial, – Industrial, – Commercial Commercial 51-85151-** ...

Page 8

... Document Title: CY2DL818 1:8 Clock Fanout Buffer Document Number: 38-07058 Rev. ECN No. Issue Date ** 115151 05/30/02 *A 117611 09/16/02 *B 122745 12/15/02 Document #: 38-07058 Rev. *B Orig. of Change Description of Change EHX New Data Sheet RGL Changed the figure cross reference in page 2 and added a note 6 in page 5 RBI Added power-up requirements to maximum ratings information. ...

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