cy2dp818 Cypress Semiconductor Corporation., cy2dp818 Datasheet

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cy2dp818

Manufacturer Part Number
cy2dp818
Description
1 8 Clock Fanout Buffer
Manufacturer
Cypress Semiconductor Corporation.
Datasheet

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Cypress Semiconductor Corporation
Document #: 38-07061 Rev. *A
Features
Block Diagram
• Low-voltage operation V
• 1:8 fanout
• Single-input-configurable for LVDS, LVPECL, or LVTTL
• 8 pair of LVPECL outputs
• Drives a 50-ohm load
• Low input capacitance
• Low output skew
• Low propagation delay Typical (tpd < 4 ns)
• Industrial versions available
• Package available include: TSSOP
• Does not exceed Bellcore 802.3 standards
• Operation at
INPUT A
INPUT B
InConfig
(LVPECL / LVDS / LVTTL)
INPUT
350 MHz–700 Mbps
DD
= 3.3V
OUTPUT
(LVPECL)
3901 North First Street
Q5A
Q3A
Q3B
Q4A
Q4B
Q5B
Q6A
Q6B
Q7A
Q7B
Q8A
Q8B
Q1A
Q1B
Q2A
Q2B
Description
This Cypress series of network circuits are produced using
advanced 0.35-micron CMOS technology, achieving the
industry’s fastest logic.
The Cypress CY2DP818 fanout buffer features a single LVDS
or a single-ended LVTTL-compatible input and eight LVPECL
output pairs.
Designed for data-communications clock-management appli-
cations, the large fanout from a single input reduces loading
on the input clock.
The CY2DP818 is ideal for both level translations from
single-ended to LVPECL and/or for the distribution of
LVPECL-based clock signals.
The Cypress CY2DP818 has configurable input functions. The
input is user configurable via the Inconfig pin for single ended
or differential input.
Pin Configuration
INPUT A
INPUT B
InConfig
GND
GND
VDD
GND
GND
GND
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
San Jose
1:8 Clock Fanout Buffer
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
38-pin TSSOP
CA 95134
ComLink™ Series
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
Revised July 9, 2002
Q3B
Q8A
GND
Q1A
Q1B
Q2A
Q2B
Q3A
Q4A
Q4B
VDD
Q5A
Q6A
Q6B
Q7A
Q7B
Q8B
GND
Q5B
CY2DP818
408-943-2600
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cy2dp818 Summary of contents

Page 1

... Description This Cypress series of network circuits are produced using advanced 0.35-micron CMOS technology, achieving the industry’s fastest logic. The Cypress CY2DP818 fanout buffer features a single LVDS or a single-ended LVTTL-compatible input and eight LVPECL output pairs. Designed for data-communications clock-management appli- cations, the large fanout from a single input reduces loading on the input clock ...

Page 2

... Input toggling 50% Duty Cycle, Outputs Disabled, not connected to VTT fL=100 MHz Single-ended, non-inverting, inverting, void of bias resistors Low-voltage differential signaling Low-voltage pseudo (positive) emitter coupled logic ComLink™ Series CY2DP818 Description Ground Power Supply Differential input pair or single line. LVPECL/LVDS default. See InConfig, below. ...

Page 3

... Guaranteed Logic Low Level V = Max Max Max (Max Min –18mA DD IN ComLink™ Series CY2DP818 True Invert Invert True Min. Typ. Max. Unit 100 600 mV IVIDI/2 2.4–(IVIDI/ 0 ±10 ± ±10 ±20 ...

Page 4

... User defined by VTT RTT Max GND DD OUT Driver Design = 3.3V ±5%, Temperature = –40°C to +85°C) DD Description Conditions 45%–55% duty cycle Standard load circuit ComLink™ Series CY2DP818 Min. Typ. Max. Unit 1000 3600 mV 300 mV 300 1200 ps 2.1 3.0 V 0.8 1.3 V –125 – ...

Page 5

... V D iffe re n tia 150 GND 150 VOC Standard Termination Next Device V I(A) 2.0V V I(B) 1.6V and t 1 ns; pulse rerate = 50 Mpps; pulse width = ComLink™ Series CY2DP818 TPA 50 TPC VDD-2V 50 TPB [2,3,4,5] TPA 50 TPC 50 TPB VOD [2,3,4,5] 0.2 ns. – Page [+] Feedback ...

Page 6

... LVPECL or LVDS differential input value. Document #: 38-07061 Rev. *A TPA 150 10pF TPC GND 150 TPB Standard Termination 1.4V 1.0V 0. & ComLink™ Series CY2DP818 50 VDD-2V 50 100% 80% 20 [2,3,4, fig [7] Figure 5. Page [+] Feedback ...

Page 7

... Package Type 38-pin TSSOP 38-pin TSSOP–Tape and Reel 38-pin TSSOP 38-pin TSSOP–Tape and Reel 38-lead TSSOP (4.40 mm Body) Z38 ComLink™ Series CY2DP818 Product Flow Industrial, – Industrial, – Commercial Commercial 51-85151-** Page ...

Page 8

... Document Title: CY2DP818 1:8 Clock Fanout Buffer Document Number: 38-07061 Issue REV. ECN NO. Date ** 107086 06/07/01 *A 115913 07/11/02 Document #: 38-07061 Rev. *A Orig. of Change Description of Change IKA New Data Sheet CTK IC, VCM, VOC, Rise/Fall Time Fmax (20) ComLink™ Series CY2DP818 Page [+] Feedback ...

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