cy29658 Cypress Semiconductor Corporation., cy29658 Datasheet

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cy29658

Manufacturer Part Number
cy29658
Description
2.5v Or 3.3v 200-mhz 10-output Zero Delay Buffer
Manufacturer
Cypress Semiconductor Corporation.
Datasheet

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Cypress Semiconductor Corporation
Document #: 38-07478 Rev. **
Features
• Output frequency range: 50 MHz to 200 MHz
• Input frequency range: 50 MHz to 200 MHz
• 2.5V or 3.3V operation
• Ten clock outputs: drive up to 20 clock lines
• One Feedback output
• LVPECL reference clock input
• 150-ps max output-output skew
• Phase-locked loop (PLL) bypass mode
• Spread Aware
• Output enable/disable
• Pin-compatible with MPC9658 and MPC958
• Industrial temperature range: –40°C to +85°C
• 32-Pin 1.0mm TQFP package
Block Diagram
PECL_C LK
PEC L_CLK#
VC O _SEL
BYPASS#
M R/O E#
PLL_EN
FB_IN
Detector
Phase
LPF
2.5V or 3.3V 200-MHz 10-Output Zero Delay Buffer
200-480M
VC O
/2
3901 North First Street
/2
FB_O UT
Q (0:8)
Q 9
Description
The CY29658 is a low-voltage high-performance 200-MHz
PLL-based zero delay buffer designed for high-speed clock
distribution applications. The CY29658 features an LVPECL
reference clock input and provides ten outputs plus one
feedback output. VCO output divides by two or four per
VCO_SEL
LVCMOS-compatible output can drive 50
parallel-terminated transmission lines. For series-terminated
transmission lines, each output can drive one or two traces
giving the device an effective fanout of 1:20.
The PLL is ensured stable given that the VCO is configured to
run between 200 MHz to 500 MHz. This allows a wide range
of output frequencies from 50 MHz to 200 MHz. For normal
operation, the external feedback input, FB_IN, is connected to
the feedback output, FB_OUT. The internal VCO is running at
multiples of the input reference clock set by the feedback
divider (see Frequency Table).
When PLL_EN is LOW, PLL is bypassed and the reference
clock directly feeds the output dividers. This mode is fully static
and the minimum input clock frequency specification does not
apply. When BYPASS# is set LOW, PLL and output dividers
are bypassed resulting in a 1:11 LVPECL to LVCMOS high
performance fanout buffer. For normal PLL operation, both
PLL_EN and BYPASS# are set HIGH.
Pin Configuration
P E C L_C LK #
P E C L_C LK
B Y P A S S #
M R /O E#
P LL_E N
setting
San Jose
F B _IN
A V D D
A V SS
1
2
3
4
5
6
7
8
,
(see
CA 95134
C Y 29658
Function
Revised May 14, 2003
24
23
22
21
20
19
18
17
Table).
408-943-2600
Q 2
V D D Q
Q 3
V S S
Q 4
V D D Q
Q 5
V S S
CY29658
series- or
Each

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cy29658 Summary of contents

Page 1

... PLL_EN Cypress Semiconductor Corporation Document #: 38-07478 Rev. ** Description The CY29658 is a low-voltage high-performance 200-MHz PLL-based zero delay buffer designed for high-speed clock distribution applications. The CY29658 features an LVPECL reference clock input and provides ten outputs plus one feedback output. VCO output divides by two or four per ...

Page 2

... VCO 1 Bypass mode, PLL disabled. The input clock connects to the output dividers Bypass mode with PLL and output dividers bypassed. The input clock connects to the outputs. Outputs enabled CY29658 Description [2,3] [2,3] [2,3] Input Frequency Range (AVDD = 2.5V) 100 MHz to 200 MHz 50 MHz to 100 MHz ...

Page 3

... Outputs loaded @ 100 MHz (V = 3.3V ± 5 –40°C to +85° Condition LVCMOS LVCMOS LVPECL [4] LVPECL [ [ – Alternatively, each output drives up to two 50 TT CY29658 Min. Max. Unit –0.3 5.5 V 2.375 3.465 –0 0 200 ...

Page 4

... DD A Condition 2 Feedback 4 Feedback Bypass mode (BYPASS Parameters are guaranteed by characterization and are not 100% tested impacts static phase offset t( ). CMR PP CY29658 Min. Typ. Max. – – –100 – – 100 – – 7 – – ...

Page 5

... Feedback 4 Feedback I/O same VDD ohm ohm ohm T VTT Figure 1. AC Test Reference for V DD PECL_CLK VCMR PECL_CLK VDD Qn VDD/2 GND Figure 3. Propagation Delay t CY29658 [7] Min. Typ. Max. 40 – 60 500 – 1000 1.2 – VDD - 0.9 100 – 200 50 – 125 45 – ...

Page 6

... The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. VDD VDD/2 GND Figure 5. Output-to-Output Skew t Package Type CY29658 VDD VDD/2 GND VDD VDD/2 GND ...

Page 7

... Document History Page Document Title:CY29658 2.5V or 3.3V 200-MHz 10-Output Zero Delay Buffer Document Number: 38-07478 Issue Rev. ECN No. Date ** 126716 05/19/03 Document #: 38-07478 Rev. ** Orig. of Change RGL New Data Sheet CY29658 Description of Change Page ...

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