cy29976 Cypress Semiconductor Corporation., cy29976 Datasheet

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cy29976

Manufacturer Part Number

cy29976

Description

3.3v, 125-mhz, Multi-output Zero Delay Buffer

Manufacturer

Cypress Semiconductor Corporation.

Datasheet

1.CY29976.pdf (10 pages)

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Company:

Bonase Electronics (HK) Co., Limited

Bonase Electronics (HK) Co., Limited

Part Number:

cy29976AI

Manufacturer:

CY

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Part Number:

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Cypress Semiconductor Corp

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BOSTOCK HK LIMITED

Part Number:

cy29976AIT

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Cypress Semiconductor Corp

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Company:

Bonase Electronics (HK) Co., Limited

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Part Number:

cy29976AXI

Manufacturer:

Microchip

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Company:

BOSTOCK HK LIMITED

BOSTOCK HK LIMITED

Part Number:

cy29976AXI

Manufacturer:

Cypress Semiconductor Corp

Quantity:

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Company:

BOSTOCK HK LIMITED

BOSTOCK HK LIMITED

Part Number:

cy29976AXIT

Manufacturer:

Cypress Semiconductor Corp

Quantity:

10 000

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Download datasheet (107Kb)

76

Features

Cypress Semiconductor Corporation

Document #: 38-07413 Rev. *A

• Output frequency up to 125 MHz

• Supports PowerPC

• 12 clock outputs: frequency configurable

• Configurable Output Disable

• Two reference clock inputs for dynamic toggling

• Oscillator or PECL reference input

• Spread spectrum compatible

• Glitch-free output clocks transitioning

• 3.3V power supply

• Pin compatible with SC973X

• Industrial temperature range: –40°C to +85°C

• 52-Pin TQFP package

Block Diagram

FB_SEL(0:2)

PECL_CLK#

PECL_CLK

TCLK_SEL

SELC(0,1)

VCO_SEL

SELA(0,1)

SELB(0,1)

REF_SEL

INV_CLK

PLL_EN

MR#/OE

SDATA

TCLK0

TCLK1

FB_IN

SCLK

Power-On

Reset

0

1

2

2

2

3

Detector

®

Phase

, and Pentium

Output Disable

Data Generator

Circuitry

/2, /6, /4, /12

/2, /6, /4, /10

/4, /6, /8, /10

/8, /2, /6, /4

Sync Pulse

LPF

VCO

3.3V, 125-MHz, Multi-Output Zero Delay Buffer

12

0

1

®

processors

•

3901 North First Street

D Q

D Q

D Q

D Q

D Q

D Q

Sync

Sync

Sync

Sync

Sync

Sync

Frz

Frz

Frz

Frz

Frz

Frz

Table 1. Frequency Table

Note:

.

1.

QA0

QA1

QA2

QA3

QB0

QB1

QB2

QB3

QC0

QC1

QC2

QC3

FB_OUT

SYNC

VC0_SEL

x = the reference input frequency, 200MHz < F

0

0

0

0

0

0

0

0

1

1

1

1

1

1

1

1

PECL_CLK#

•

PECL_CLK

TCLK_SEL

Pin Configuration

REF_SEL

FB_SEL2

MR#/OE

PLL_EN

SDATA

TCLK0

TCLK1

SCLK

San Jose

VDD

VSS

FB_SEL2

0

0

0

0

1

1

1

1

0

0

0

0

1

1

1

1

1

2

3

4

5

6

7

8

9

10

11

12

13

52 51 50 49 48 47 46 45 44 43 42 41 40

14 15 16 17 18 19 20 21 22 23 24 25 26

•

CY29976

FB_SEL1

[1]

CA 95134

0

0

1

1

0

0

1

1

0

0

1

1

0

0

1

1

Revised December 27, 2002

FB_SEL0

VCO

•

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

< 480MHz

CY29976

39

38

37

36

35

34

33

32

31

30

29

28

27

408-943-2600

VSS

QB0

VDDC

QB1

VSS

QB2

VDDC

QB3

FB_IN

VSS

FB_OUT

VDDC

FB_SEL0

F

12x

16x

20x

12x

16x

20x

10x

10x

VCO

8x

8x

4x

6x

8x

4x

6x

8x

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