cy24206 Cypress Semiconductor Corporation., cy24206 Datasheet
cy24206
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cy24206 Summary of contents
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... OUTPUT MULTIPLEXER CLK1 AND DIVIDERS CLK2 REFCLK CLK3 (-2, -3,-4) AVDD AVSS VSS VSSL CY24206-2,3,4 16-pin TSSOP XOUT 1 16 XIN 2 15 VDD FS2 14 AVDD 3 FS1 13 ...
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... CLK2 CLK3 (-2, -3,- (CLK1/3) 27 (CLK1/3) 81.081 27.027 (CLK1/3) 27.027 (CLK1/3) 74.17582 24.725 (CLK1/3) 74.17582 (CLK1) 74.25 24.75 (CLK1/3) 74.25 (CLK1 (CLK1/3) 81.081 27 27.027 (CLK1/3) 74.1758 27 74.175 (CLK1) 74.25 27 74.25 (CLK1) Description CY24206 REFCLK Units 27 MHz 27 MHz 27 MHz 27 MHz 27 MHz 27 MHz 27 MHz 27 MHz Page [+] Feedback ...
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... Output Clock Edge Rate, Measured from 20 pF. See Figure 2. DD LOAD Output Clock Edge Rate, Measured from 80 pF. See Figure 2. DD LOAD CLK1, CLK2 Peak-Peak period jitter DUT GND CY24206 Max. Unit 7.0 V 7.0 V 125 ° 0 Typ. ...
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... Figure (0 Ordering Information Ordering Code Package Name CY24206ZC-2 Z16 CY24206ZC-2T Z16 CY24206ZC-3 Z16 CY24206ZC-3T Z16 CY24206ZC-4 Z16 CY24206ZC-4T Z16 Lead Free CY24206ZXC-4 Z16 CY24206ZXC-4T Z16 Document #: 38-07451 Rev Figure 1. Duty Cycle Definitions 80 20 /t3 ...
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... DIMENSIONS IN MM[INCHES] MIN. REFERENCE JEDEC MO-153 6.25[0.246] PACKAGE WEIGHT 0.05 gms 6.50[0.256] Z16.173 ZZ16.173 LEAD FREE PKG. 0.25[0.010] 1.10[0.043] MAX. BSC GAUGE 0°-8° PLANE 0.076[0.003] SEATING PLANE CY24206 MAX. PART # STANDARD PKG. 0.50[0.020] 0.09[[0.003] 0.70[0.027] 0.20[0.008] 51-85091-*A Page [+] Feedback ...
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... Document History Page Document Title: CY24206 MediaClock™ DTV, STB Clock Generator Document Number: 38-07451 REV. ECN NO. Issue Date ** 120901 12/10/02 *A 123046 03/03/03 *B 270029 See ECN Document #: 38-07451 Rev. *B Orig. of Change Description of Change CKN New data sheet CKN Added –4 to data sheet RGL ...