cy24130-2 Cypress Semiconductor Corporation., cy24130-2 Datasheet

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... HOTLink II™ SMPTE Receiver Training Clock Features • Integrated phase-locked loop • Low-jitter, high-accuracy outputs • 3.3V operation Part Number Outputs Input Frequency CY24130 MHz (Driven Reference) CY24130 MHz (Crystal Reference) Logic Block Diagram XIN Q OSC. Φ VCO XOUT P PLL ...

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... OFF, pulled low 0 OFF, pulled low 1 OFF, pulled low Min. –0.5 – – AV – 0 Min. Typ. 3.135 3.3 0 – – – – 27 – 18 CY24130 REFCLK Units 27 MHz 27 MHz 27 MHz 27 MHz 27 MHz 27 MHz 27 MHz 27 MHz Max. Unit 7.0 V 7.0 V 125 ° 0.3 ...

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... See Figure 2. DD LOAD Output Clock Edge Rate, Measured from 80 pF. See Figure 2. DD LOAD CLKA Peak-Peak Period Jitter DUT GND Figure 1. Duty Cycle Definitions CY24130 Min. Typ. Max. Unit 12 24 – – mA µA – µ ...

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... PIN 1 ID DIMENSIONS IN MM[INCHES] MIN. REFERENCE JEDEC MO-153 6.25[0.246] PACKAGE WEIGHT 0.05 gms 6.50[0.256] Z16.173 ZZ16.173 LEAD FREE PKG. 0.25[0.010] 1.10[0.043] MAX. BSC GAUGE 0°-8° PLANE 0.076[0.003] SEATING PLANE CY24130 Operating Voltage 3.3V 3.3V 3.3V 3.3V MAX. PART # STANDARD PKG. 0.50[0.020] 0.09[[0.003] 0.70[0.027] ...

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... Document History Page Document Title: CY24130 HOTLink II™ SMPTE Receiver Training Clock Document Number: 38-07711 REV. ECN NO. Issue Date ** 314514 See ECN Document #: 38-07711 Rev. ** Orig. of Change Description of Change RGL New Data Sheet CY24130 Page [+] Feedback ...