cy241v08a-11 Cypress Semiconductor Corporation., cy241v08a-11 Datasheet
cy241v08a-11
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cy241v08a-11 Summary of contents
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... Application compatibility for a wide variety of designs Output VCXO Control Frequencies One copy of 54 MHz linear PLL OUTPUT DIVIDER VSS VDD • 3901 North First Street • San Jose CY241V08A-11 Curve Other Features Pinout-compatible with CY2411 54 MHz , CA 95134 • 408-943-2600 Revised April 22, 2004 [+] Feedback ...
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... Pin Descriptions Name Pin Number XIN 1 Reference crystal input. VDD 2,5 Voltage supply. VCXO 3 Input analog control for VCXO. VSS 4,7 Ground. 54MHz 6 54MHz clock output. XOUT 8 Reference crystal output. Document #: 38-07654 Rev. *A CY241V08A-11 Description Page [+] Feedback ...
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... Output Clock Edge Rate, Measured from 20 pF. See Figure 2. DD LOAD Output Clock Edge Rate, Measured from 80 pF. See Figure 2. DD LOAD Peak-to-peak period jitter CY241V08A-11 Min. Typ. Max. Unit – 13.5 – MHz – 14 – – – 25 ...
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... V 50 Figure 1. Duty Cycle Definition 80 20 /t3 (0 Operating Package Type Range Commercial CY241V08A-11 Outputs C LOAD /t4 DD Operating Voltage Features 3.3V Linear VCXO control curve 3.3V Linear VCXO control curve Page [+] Feedback ...
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... S08.15 STANDARD PKG. SZ08.15 LEAD FREE PKG. SEATING PLANE 0.061[1.549] 0.068[1.727] 0.004[0.102] 0.004[0.102] 0°~8° 0.016[0.406] 0.0098[0.249] 0.035[0.889] CY241V08A-11 MAX. PART # 0.010[0.254] X 45° 0.016[0.406] 0.0075[0.190] 0.0098[0.249] 51-85066-*C Page [+] Feedback ...
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... Document History Page Document Title: CY241V08A-11 MPEG Clock Generator with VCXO Document Number: 38-07654 Issue REV. ECN NO. Date ** 214071 See ECN *A 220461 See ECN Document #: 38-07654 Rev. *A Orig. of Change Description of Change RGL New Data Sheet RGL Minor Change: To post on web CY241V08A-11 ...