cy241v08a-01 Cypress Semiconductor Corporation., cy241v08a-01 Datasheet

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cy241v08a-01

Manufacturer Part Number
cy241v08a-01
Description
Mpeg Clock Generator With Vcxo
Manufacturer
Cypress Semiconductor Corporation.
Datasheet
Cypress Semiconductor Corporation
Document #: 38-07656 Rev. *C
Features
CY241V08A-01
CY241V08A-04
• Integrated phase-locked loop (PLL)
• Low-jitter, high-accuracy outputs
• VCXO with analog adjust
• 3.3V operation
• Compatible with MK3727 (–1, –4)
• Application compatibility for a wide variety of designs
• Enables design compatibility
• Lower drive strength settings (CY241V08A–04)
CY241V08A-01,-04 Logic Block Diagram
Number
Pin Configurations
Part
13.5 XIN
XOUT
VCXO
Outputs
1
1
OSC
13.5-MHz pullable crystal input per
Cypress specification
13.5-MHz pullable crystal input per
Cypress specification
Q
Input Frequency Range
Φ
CY241V08A-01,-04
VCXO
VDD
VSS
XIN
P
8-pin SOIC
PLL
1
2
3
4
VCO
VDD VSS
198 Champion Court
8
7
6
5
XOUT
NC or VSS
NC or VDD
27 MHz
MPEG Clock Generator with VCXO
DIVIDERS
OUTPUT
Benefits
1 copy of 27 MHz linear
1 copy of 27 MHz linear
• Digital VCXO control
• Second source for existing designs
• Highest-performance PLL tailored for multimedia applica-
• Meets critical timing requirements in complex system
Frequencies
tions
designs
Output
27 MHz
San Jose
VCXO Control
,
CA 95134-1709
Curve
CY241V08A-01,04
Revised December 14, 2005
Compatible with MK3727
Same as CY241V08A-01
except lower drive
strength settings
CY241V8A-01
Other Features
408-943-2600
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cy241v08a-01 Summary of contents

Page 1

... Low-jitter, high-accuracy outputs • VCXO with analog adjust • 3.3V operation • Compatible with MK3727 (–1, –4) • Application compatibility for a wide variety of designs • Enables design compatibility • Lower drive strength settings (CY241V08A–04) CY241V08A-01,-04 Logic Block Diagram 13.5 XIN Φ OSC Q XOUT VCXO ...

Page 2

... XIN 1 Reference crystal input VDD 2 Voltage supply VCXO 3 Input analog control for VCXO VSS 4 Ground 27 MHz 5 27-MHz clock output NC/VDD 6 No connect or voltage supply NC/VSS 7 No connect or ground XOUT 8 Reference crystal output Document #: 38-07656 Rev. *C CY241V08A-01,04 CY241V8A-01 Description Page [+] Feedback ...

Page 3

... No external series resistor assumed High side Low side Description Description – 0.5V 3. 0.5V 3. Except XIN, XOUT pins Low Side High Side CY241V08A-01,04 CY241V8A-01 Min. Typ. Max. Unit – 13.5 – MHz – 14 – pF Ω – – – – ...

Page 4

... CLOAD = 15 pF See Figure 2. DD Peak-to-peak period jitter 0.1 µF C DUT GND 50 Figure 1. Duty Cycle Definition CY241V08A-01,04 CY241V8A-01 Min. Typ. Max. Unit 0.8 1.4 – V/ns 0.8 1.4 – V/ns 0.7 1.1 – V/ns 0.7 1.1 – V/ns – ...

Page 5

... S08.15 STANDARD PKG. SZ08.15 LEAD FREE PKG. SEATING PLANE 0.061[1.549] 0.068[1.727] 0.004[0.102] 0.004[0.102] 0°~8° 0.016[0.406] 0.0098[0.249] 0.035[0.889] CY241V08A-01,04 CY241V8A-01 Operating Voltage Features 3.3V Linear VCXO control curve 3.3V Linear VCXO control curve 3.3V Linear VCXO control curve 3 ...

Page 6

... Document History Page Document Title: CY241V08A-01,04/ CY241V8A-01MPEG Clock Generator with VCXO Document Number: 38-07656 REV. ECN NO. Issue Date ** 214069 See ECN *A 220404 See ECN *B 393122 See ECN *C 414184 See ECN Document #: 38-07656 Rev. *C Orig. of Change Description of Change RGL New Data Sheet ...

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