cy25560 Cypress Semiconductor Corporation., cy25560 Datasheet - Page 3

• Manufacturer Part Number: cy25560
• Description: Spread Spectrum Clock Generator
• Manufacturer: Cypress Semiconductor Corporation.

Document #: 38-07425 Rev. *D
Tri-level Logic
With binary logic, four states can be programmed with two
control lines whereas three-level logic can program nine logic
states using two control lines. Three-level logic in the
CY25560 is implemented by defining a third logic state in
addition to the standard logic “1” and “0.” Pins 6 and 7 of the
CY25560 recognize a logic state by the voltage applied to the
respective pin. These states are defined as “0” (Low), “M”
(Middle), and “1” (One). Each of these states have a defined
voltage range that is interpreted by the CY25560 as a “0”, “M”
or “1” logic state. Refer to Table 2 for voltage ranges for each
logic state. The CY25560 has two equal value resistor dividers
connected internally to Pins 6 and 7 that produce the default
“M” (Middle) state if these pins are left unconnected (NC). Pins
6 and/or 7 can be tied directly to ground or V
Logic “0” or “1” state, respectively.
SSCG Theory of Operation
The CY25560 is a PLL-type clock generator using a propri-
etary Cypress design. By precisely controlling the bandwidth
of the output clock, the CY25560 becomes a Low-EMI clock
generator. The theory and detailed operation of the CY25560
will be discussed in the following sections.
EMI
All digital clocks generate unwanted energy in their harmonics.
Conventional digital clocks are square waves with a duty cycle
that is very close to 50%. Because of this 50/50 duty cycle,
digital clocks generate most of their harmonic energy in the
odd harmonics, i.e., third, fifth, seventh, etc. It is possible to
reduce the amount of energy contained in the fundamental
and odd harmonics by increasing the bandwidth of the funda-
mental clock frequency. Conventional digital clocks have a
very high Q factor, which means that all of the energy at that
frequency is concentrated in a very narrow bandwidth, conse-
quently, higher energy peaks. Regulatory agencies test
electronic equipment by the amount of peak energy radiated
from the equipment. By reducing the peak energy at the funda-
mental and harmonic frequencies, the equipment under test is
able to satisfy agency requirements for EMI. Conventional
methods of reducing EMI have been to use shielding, filtering,
multilayer PCBs, etc. The CY25560 uses the approach of
reducing the peak energy in the clock by increasing the clock
bandwidth, and lowering the Q.
S1 = "0" (GND)
SSCC = "1"
S0 = "M" (N/C)
CY25560
7
6
5
S0
VDD
S1
Figure 1. Three-level Logic Examples
DD
to program a
S1 = "0" (GND)
SSCC = "1"
CY25560
S0 = "1"
7
6
5
SSCG
SSCG uses a patented technology of modulating the clock
over a very narrow bandwidth and controlled rate of change,
both peak and cycle to cycle. The CY25560 takes a narrow
band digital reference clock in the range of 25–100 MHz and
produces a clock that sweeps between a controlled start and
stop frequency and precise rate of change. To understand
what happens to a clock when SSCG is applied, consider a
65-MHz clock with a 50% duty cycle. From a 65-MHz clock we
know the following:
If this clock is applied to the Xin/CLK pin of CY25560, the
output clock at pin 4 (SSCLK) will be sweeping back and forth
between two frequencies. These two frequencies, F1 and F2,
are used to calculate to total amount of spread or bandwidth
applied to the reference clock at pin 1. As the clock is making
the transition from F1 to F2, the amount of time and sweep
waveform play a very important role in the amount of EMI
reduction realized from an SSCG clock.
The modulation domain analyzer is used to visualize the
sweep waveform and sweep period. Figure 2 shows the
modulation profile of a 65 MHz SSCG clock. Notice that the
actual sweep waveform is not a simple sine or sawtooth
waveform. Figure 2 also shows a scan of the same SSCG
clock using a spectrum analyzer. In this scan you can see
a 6.48-dB reduction in the peak RF energy when using the
SSCG clock.
Modulation Rate
Spectrum Spread Clock Generators utilize frequency
modulation (FM) to distribute energy over a specific band of
frequencies. The maximum frequency of the clock (Fmax) and
minimum frequency of the clock (Fmin) determine this band of
frequencies. The time required to transition from Fmin to Fmax
and back to Fmin is the period of the Modulation Rate, Tmod.
Modulation Rates of SSCG clocks are generally referred to in
terms of frequency or Fmod = 1/Tmod.
The input clock frequency, Fin, and the internal divider count,
Cdiv, determine the Modulation Rate. In some SSCG clock
generators, the selected range determines the internal divider
count. In other SSCG clocks, the internal divider count is fixed
over the operating range of the part. The CY25560 has a fixed
divider count of 1166.
Clock Frequency = fc = 200 MHz
Clock Period = Tc =1/200 MHz = 5.0 ns.
S0
VDD
S1
VDD
S0 = "1"
S1 = "1"
SSCC = "1"
CY25560
5 0 %
T c = 5 .0 n s
7
6
5
CY25560
S1
S0
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5 0 %
VDD
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