cy2546 Cypress Semiconductor Corporation., cy2546 Datasheet
cy2546
Related parts for cy2546
cy2546 Summary of contents
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... Programmable Spread Spectrum with Center and Down Spread option and Lexmark modulation profile • Two VDD core voltage options: — 2.5V, 3.0V, and 3.3V for CY2544 — 1.8V for CY2546 • Selectable output voltages: — 2.5V, 3.0V, and 3.3V for CY2544 — 1.8V for CY2546 • Frequency Select feature with option to select eight different frequencies • ...
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... Power Supply for Output Bank3 (CLK7, CLK8, CLK9) output Output Programmable Output Clock Power Power Supply Ground for Output Bank 3 CY2544 CY2546 GND 17 CLK8 VDD_CLK_B3 16 CY2546 24LD QFN 15 CLK7/SSON VDD_CLK_B2 14 13 CLK6 Description Page [+] Feedback ...
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... Pin Description - CY2544 (2.5V, 3.0V or 3.3V VDD) Pin Number Name 19 GND 20 CLK9 21 EXCLKIN 22 VDD 23 XOUT 24 XIN Pin Description - CY2546 (1.8V VDD_CORE) Pin Number Name 1 GND 2 CLK1 3 VDD_CLK_B1 4 PD#/OE 5 VDD_CORE 6 CLK2 7 GND 8 CLK3/FS0 9 PD#/OE/FS1 10 CLK4/FS2 11 CLK5 12 GND 13 CLK6 14 VDD_CLK_B2 15 CLK7/SSON 16 VDD_CLK_B3 17 CLK8 18 GND 19 GND 20 CLK9 21 EXCLKIN ...
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... Document #: 001-12563 Rev. *A PRELIMINARY The input to the CY2544 and CY2546 is either a crystal or a clock signal. The input frequency range for crystals is 8 MHz to 48 MHz, and for clock signals is 8 MHz to 166 MHz. In addition, there is a separate input for a clock reference. ...
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... Output Driver Voltage for Bank 1, 2 and 3 Operating at 3.3V (CY2544) DD_CLK_BX V Output Driver Voltage for Bank 1, 2 and 3 Operating at 3.0V (CY2544) DD_CLK_BX V Output Driver Voltage for Bank 1, 2 and 3 Operating at 2.5V (CY2544) DD_CLK_BX V Output Driver Voltage for Bank 1, 2 and 3 Operating at 1.8V (CY2546) DD_CLK_BX T Commercial Ambient Temperature AC T Industrial Ambient Temperature AI C ...
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... Configuration dependent. See “Configuration Example for Jitter,” on page 6 Max Jitter (ps) on Max Jitter (ps) on Output 2 (27 MHz) Output 3 (166 MHz) 155 255 135 225 770 580 535 575 CY2544 CY2546 Min. Typ. Max. Unit 8 – 48 MHz 8 – 166 MHz 3 – 166 MHz 45 ...
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... Fmax Maximum Frequency R1(max) Maximum Motional Resistance (ESR) C0(max) Maximum Shunt Capacitance CL(max) Maximum Parallel Load Capacitance DL(max) Maximum Crystal Drive Level Document #: 001-12563 Rev. *A PRELIMINARY Description Description CY2544 CY2546 Range 1 Range 2 Range 3 Unit MHz MHz Ω 135 50 30 ...
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... Output Document #: 001-12563 Rev. *A PRELIMINARY Figure 1. Test and Measurement Setup 0.1 μF C DUT GND Figure 2. Duty Cycle Definition ( CY2544 CY2546 Outputs LOAD Page [+] Feedback ...
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... QFN - Tape & Reel CY2546Ixxx 24-pin QFN CY2546IxxxT 24-pin QFN -Tape & Reel CY2546FI 24-pin QFN CY2546FIT 24-pin QFN -Tape & Reel Note 2. xxx Indicates Factory Programmable are factory programmed configurations. For more details, contact your local Cypress FAE or Cypress Sales Representative. ...
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... Cypress against all charges. PRELIMINARY SIDE VIEW 0.05 C 1.00 MAX. 0.23±0.05 0.05 MAX. 0.80 MAX. 0.20 REF. 2.45 2.49 2.55 0.42±0.18 0°-12° (4X) C SEATING PLANE CY2544 CY2546 BOTTOM VIEW PIN1 ID 2.49 0. 0.45 SOLDERABLE EXPOSED PAD 0.30-0.50 0.50 2.45 2.55 51-85203-*A Page [+] Feedback ...
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... Document History Page Document Title: CY2544/CY2546 Quad PLL Programmable Clock Generator with Spread Spectrum Document Number: 001-12563 REV. ECN NO. Issue Date ** 690257 See ECN *A 790516 See ECN Document #: 001-12563 Rev. *A PRELIMINARY Orig. of Description of Change Change RGL New Data Sheet RGL Separated the Pin Configuration drawing into two to show the difference between CY2544 and CY2546 pin outs ...