cy2309szi-1t Cypress Semiconductor Corporation., cy2309szi-1t Datasheet

cy2309szi-1t

Manufacturer Part Number

cy2309szi-1t

Description

Low-cost 3.3v Zero Delay Buffer

Manufacturer

Cypress Semiconductor Corporation.

Datasheet

1.CY2309SZI-1T.pdf (14 pages)

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Cypress Semiconductor Corporation

Document #: 38-07140 Rev. *G

Features

Functional Description

The CY2309 is a low-cost 3.3V zero delay buffer designed to

distribute high-speed clocks and is available in a 16-pin SOIC

or TSSOP package. The CY2305 is an 8-pin version of the

Block Diagram

• 10-MHz to 100-/133-MHz operating range, compatible

• Zero input-output propagation delay

• 60 ps typical cycle-to-cycle jitter (high drive)

• Multiple low-skew outputs

• Compatible with Pentium

• Test Mode to bypass phase-locked loop (PLL) (CY2309

• Available in space-saving 16-pin 150-mil SOIC or

• 3.3V operation

• Industrial temperature available

REF

with CPU and PCI bus frequencies

— 85 ps typical output-to-output skew

— One input drives five outputs (CY2305)

— One input drives nine outputs, grouped as 4 + 4 + 1

only [see “Select Input Decoding” on page 2])

4.4-mm TSSOP packages (CY2309), and 8-pin, 150-mil

SOIC package (CY2305)

(CY2309)

PLL



-based systems

Select Input

Decoding

•

MUX

3901 North First Street

Low-Cost 3.3V Zero Delay Buffer

CY2309. It accepts one reference input, and drives out five

low-skew clocks. The -1H versions of each device operate at

up to 100-/133-MHz frequencies, and have higher drive than

the -1 devices. All parts have on-chip PLLs which lock to an

input clock on the REF pin. The PLL feedback is on-chip and

is obtained from the CLKOUT pad.

The CY2309 has two banks of four outputs each, which can

be controlled by the Select inputs as shown in the “Select Input

Decoding” table on page 2. If all output clocks are not required,

BankB can be three-stated. The select inputs also allow the

input clock to be directly applied to the outputs for chip and

system testing purposes.

The CY2305 and CY2309 PLLs enter a power-down mode

when there are no rising edges on the REF input. In this state,

the outputs are three-stated and the PLL is turned off, resulting

in less than 12.0 µA of current draw for commercial temper-

ature devices and 25.0 µA for industrial temperature parts. The

CY2309 PLL shuts down in one additional case as shown in

the table below.

Multiple CY2305 and CY2309 devices can accept the same

input clock and distribute it. In this case, the skew between the

outputs of two devices is guaranteed to be less than 700 ps.

The CY2305/CY2309 is available in two/three different config-

urations, as shown in the ordering information (page 10). The

CY2305-1/CY2309-1 is the base part. The CY2305-1H/

CY2309-1H is the high-drive version of the -1, and its rise and

fall times are much faster than the -1s.

CLKOUT

CLKA1

CLKA2

CLKA3

CLKA4

CLKB1

CLKB2

CLKB3

CLKB4

•

San Jose

CLKB1

CLKB2

CLKA1

CLKA2

GND

REF

Pin Configuration

CLK2

CLK1

GND

REF

SOIC/TSSOP

CA 95134

Top View

SOIC

Revised August 4, 2005

•

CLKOUT

CLK4

CLK3

CLKOUT

CLKA4

CLKA3

GND

CLKB4

CLKB3

408-943-2600

CY2305

CY2309

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