cy28800 Cypress Semiconductor Corporation., cy28800 Datasheet
cy28800
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cy28800 Summary of contents
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... Cypress Semiconductor Corporation Document #: 38-07723 Rev *B 100-MHz Differential Buffer for PCI Express Functional Description The CY28800 is a differential buffer and serves as a companion device to the CK409 or CK410 clock generator. The device is capable of distributing the Serial Reference Clock (SRC) in PCI Express and SATA implementations. ...
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... Table 1. The block write and block read protocol is outlined in Table 2 while Table 3 outlines the corresponding byte write and byte read protocol. The slave receiver address is 11011100 (DCh). Description CY28800 Page [+] Feedback ...
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... Acknowledge from slave 20 Repeat start 21:27 Slave address – 7 bits 28 Read = 1 29 Acknowledge from slave 30:37 Data byte from slave – 8 bits 38 Acknowledge from master 39 Stop CY28800 Page [+] Feedback ...
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... DIF[T/C]0 Output Enable 0 = Disabled (Tri-state Enabled Description Allow Control DIF[T/C]7 with assertion of SRC_STP 0 = Free-running 1 = Stopped with SRC_STP Allow Control DIF[T/C]6 with assertion of SRC_STP 0 = Free-running 1 = Stopped with SRC_STP Allow Control DIF[T/C]5 with assertion of SRC_STP 0 = Free-running 1 = Stopped with SRC_STP CY28800 Page [+] Feedback ...
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... Reserved Reserved Reserved Reserved Reserved Reserved Reserved Description Revision Code Bit 3 Revision Code Bit 2 Revision Code Bit 1 Revision Code Bit 0 Vendor ID Bit 3 Vendor ID Bit 2 Vendor ID Bit 1 Vendor ID Bit 0 Description Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved CY28800 Page [+] Feedback ...
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... IF the control register PWRDWN Drive Mode bit is programmed to ‘1’, all differential outputs must be driven high in less than 300 µs of the power down pin deassertion to a voltage greater than 200 mV. Tstable <1 ms Tdrive_Pwrdwn# <300 µs, >200 mV CY28800 PWRDWN Mode 0 Power Down 1 Normal 0 ...
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... Description Figure 5. Buffer Power-up State Diagram disabled via OE control, the output will always be tri-stated regardless of the SRC_STP Drive Mode register bit state. Table 5. SRC_STP Functionality OE_INV SRC_STP CY28800 [1] [6] DIFT DIFC 1 Normal Normal 0 Iref * 6 or Float Low 1 ...
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... DIFT/C outputs resuming simultaneously. If the control register tri-state bit is programmed to ‘1’ (tri-state), then all stopped DIFT outputs will be driven high within SRC_STP deassertion to a voltage greater than 200 mV CY28800 Page [+] Feedback ...
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... Document #: 38-07723 Rev * Table 6. OE Functionality OE_INV OE (Pin) OE (SMBus Bit CY28800 DIF[T/C] Tri-State Tri-State Tri-State Enabled Tri-State Enabled Tri-State Tri-State Page [+] Feedback ...
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... The PLL high bandwidth mode may be selected in two ways, via writing a ‘0’ to SMBus register bit or by asserting the HIGH_BW# pin is low or both, the device will be configured for high bandwidth operation. CY28800 Page [+] Feedback ...
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... SRC_STP asserted, Outputs Driven, PLL SRC_STP asserted, Outputs Tri-State, PLL PWRDWN asserted, Outputs driven PWRDWN asserted, Outputs Tri-stated Condition Measured at crossing point V OX Measured at crossing point V OX Single ended measurement 0.175 0.525V (Averaged) OH Measured SE CY28800 Min. Max. Unit –0.5 4.6 V –0.5 4.6 V –0 0.5 VDC DD –65 +150 ° ...
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... Ω tia lly Figure 12. Differential Clock Termination CY28800 Min. Max. Unit 140 mV –100 100 mV ...
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... Switching Waveforms V = 0.525V OH VCROSS V = 0.175V OL Figure 13. Single-Ended Measurement Points for TRise and TFall Figure 14. Single-ended Measurement Points for V Document #: 38-07723 Rev *B CY28800 TRise (CLOCK) TFall (CLOCK UDS ,V and V OVS UDS RB Page [+] Feedback ...
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... Ordering Information Ordering Code Lead Free CY28800OXC CY28800OXCT Document #: 38-07723 Rev *B T PERIOD High Duty Cycle % Package Type 48-pin SSOP 48-pin SSOP–Tape and Reel CY28800 Low Duty Cycle % Operating Range Commercial, 0° °C Commercial, 0° °C Page [+] Feedback ...
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... The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. CY28800 51-85061-*C ...
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... Document History Page Document Title: CY28800 100-MHz Differential Buffer for PCI Express and SATA Document Number: 38-07723 Rev. ECN No. Issue Date ** 299711 See ECN *A 404280 See ECN *B 465413 See ECN Document #: 38-07723 Rev *B Orig. of Change Description of Change RGL New data sheet RGL IDD 3 ...