cy28src02 Cypress Semiconductor Corporation., cy28src02 Datasheet
cy28src02
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cy28src02 Summary of contents
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... TSSOP package Pin Configuration VSS_SRC VDD_SRC SRCT2 SRCC2 SRCT1 SRCC1 VSS_SRC VDD_SRC VDD_SRC SRCT[2:1],SRCC[2:1] VSS_SRC IREF • 3901 North First Street • San Jose CY28SRC02 1 20 VDD_SRC 2 19 SDATA 3 18 SCLK XOUT 6 15 XIN ...
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... The slave receiver address is 11010010 (D2h). Description Bit 1 Start 8:2 Slave address – 7 bits 9 Write 10 Acknowledge from slave 18:11 Command Code – 8 bits 19 Acknowledge from slave 20 Repeat start 27:21 Slave address – 7 bits CY28SRC02 Description Block Read Protocol Description Page [+] Feedback ...
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... Enable- only for CY28SRC04 0 = Disable (Hi-Z Enable SRC[T/C]3 Output Enable- only for CY28SRC04 0 = Disable (Hi-Z Enable SRC[T/C]2 Output Enable- only for CY28SRC02 and CY28SRC04 0 = Disable (Hi- Enable SRC[T/C]1 Output Enable- only for CY28SRC02 and CY28SRC04 0 = Disable (Hi-Z Enable SRC[T/C]0 Output Enable- only for CY28SRC01 0 = Disable (Hi-Z Enable ...
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... Spread Spectrum Selection ‘0’ = –0.35% ‘1’ = –0.50% Reserved Reserved Reserved Reserved SRC Spread Spectrum Enable 0 = Spread off Spread on Reserved Reserved Description Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Description Reserved Reserved Reserved Reserved Reserved Reserved CY28SRC02 Page [+] Feedback ...
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... Revision Code Bit 1 Revision Code Bit 0 Vendor ID Bit 3 Vendor ID Bit 2 Vendor ID Bit 1 Vendor ID Bit 0 CY28SRC02 to operate at the wrong frequency and violate the ppm specification. For most applications there is a 300-ppm frequency shift between series and parallel crystals due to incorrect loading. Drive Shunt Cap Load Cap (max ...
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... CLe 1 ( Ce1 + Cs1 + Ci1 CL ....................................................Crystal load capacitance CLe ......................................... Actual loading seen by crystal using standard value trim capacitors Ce ..................................................... External trim capacitors Cs ..............................................Stray capacitance (terraced) Ci .......................................................... Internal capacitance (lead frame, bond wires etc.) CY28SRC02 Ci2 Pin Trace 2.8pF Ce2 Trim 27pF ...
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... JEDEC (JESD 51) At 1/8 in. Condition 3.3V ± 5% SDATA, SCLK SDATA, SCLK V DD Except Pull-ups or Pull-downs 0<V < max load and frequency PD asserted, Outputs driven PD asserted, Outputs Hi-Z CY28SRC02 Min. Max. Unit –0.5 4.6 V –0.5 4.6 V –0 0.5 VDC DD –65 +150 ° °C – ...
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... Measured from V = 0.175 0.525V OH Determined as a fraction of 2*(T – T )/( Math averages Figure 3 Math averages Figure 3 See Figure 3. Measure SE Measurement at 1.5V Measurement at 1. µs CY28SRC02 Min. Max. Unit 47.5 52.5 % 69.841 71.0 ns – 10 9.997001 10.00300 ns OX 9.997001 10.05327 ns OX 10.12800 9.872001 ...
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... MAX. BSC GAUGE PLANE 0.076[0.003] 0.05[0.002] SEATING 0.15[0.006] PLANE CY28SRC02 Product Flow Commercial, 0° to 70°C Commercial, 0° to 70°C MAX. PART # Z20.173 STANDARD PKG. ZZ20.173 LEAD FREE PKG. 0°-8° 0.50[0.020] ...
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... Document History Page Document Title: CY28SRC02 PCI-Express Clock Generator Document Number: 001-00042 REV. ECN NO. Issue Date ** 370534 See ECN *A 385834 See ECN Document #: 001-00042 Rev. *A PRELIMINARY Orig. of Change Description of Change RGL New Data Sheet RGL Swapped pin 5 and 6 CY28SRC02 Page ...