cy28508 SpectraLinear Inc, cy28508 Datasheet - Page 5

• Manufacturer Part Number: cy28508
• Description: 333 Mhz Low-voltage Differential Sscg
• Manufacturer: SpectraLinear Inc

Rev 1.0, November 24, 2006
Byte 3: Dial-a-Frequency Control Register N1 [default = 224.70 MHz, N = 86d, ODSEL = 1]
Byte 4: Dial-a-Frequency Control Register M1 [default = 224.70 MHz, M = 49d, ODSEL = 1]
Byte 5: Dial-a-Frequency Control Register N2 – Only Bit 7 is Used by the CY28508
Byte 6: Dial-a-Frequency Control Register M2 – Only Bits 6 and 7 are Used by the CY28508
Bit
Bit
Bit
Bit
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
@Pup
@Pup
@Pup
@Pup
0
1
0
1
0
1
1
0
1
1
1
1
0
0
0
1
0
0
1
1
0
0
0
0
1
1
1
1
0
0
0
0
Reserved, set = 0.
N6, MSB
N5
N4
N3
N2
N1
N0, LSB
Reserved, set = 1.
SWODSEL: Output divider select. 0 = /2, 1 = /3.
Changing the output divider causes large instantaneous changes in the CPU pulse width and
should only be changed before system operation is to occur.
M5 MSB.
M4
M3
M2
M1
M0, LSB.
UP/DN pulse width limit. During Smooth-Track, the bandwidth hence the slew rate is controlled through
limiting the pulse width of the UP/DN pulse outputs of the phase detector going to the charge pump. The
default is 0 = 20 ns and can be programmed to 1 = 40 ns, which will increase the slew rate.
Reserved, set = 0.
Reserved, set = 1.
Reserved, set = 1.
Reserved, set = 0.
Reserved, set = 0.
Reserved, set = 0.
Reserved, set = 0.
FSEL Control: 1 = HW FSEL, 0 = SW FSEL
SW FSEL: 0 = SW MN0 select, 1 = SW MN1 select. Only valid when B6b7 = 0.
Reserved, set = 1.
Reserved, set = 1.
Reserved, set = 0.
Reserved, set = 0.
Reserved, set = 0.
Reserved, set = 0.
Description
Description
Description
Description
CY28508
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