cy28rs680-2 SpectraLinear Inc, cy28rs680-2 Datasheet - Page 3

• Manufacturer Part Number: cy28rs680-2
• Description: Clock Generator For Ati Rs5xx/6xx Chipsets
• Manufacturer: SpectraLinear Inc

Rev 1.0, November 22, 2006
Pin Description
Serial Data Interface
To enhance the flexibility and function of the clock synthesizer,
a two-signal serial interface is provided. Through the Serial
Data Interface, various device functions, such as individual
clock output buffers, can be individually enabled or disabled.
The registers associated with the Serial Data Interface
initialize to their default setting upon power-up, and therefore
use of this interface is optional. Clock device register changes
are normally made upon system initialization, if any are
required. The interface cannot be used during system
operation for power management functions.
Table 1. Command Code Definition
Table 2. Block Read and Block Write Protocol
Pin No.
54, 55,
18:11
27:20
36:29
45:38
51
52
53
56
(6:5)
(4:0)
Bit
8:2
Bit
10
19
28
37
46
....
....
....
....
1
9
7
Start
Slave address – 7 bits
Write
Acknowledge from slave
Command Code – 8 bits
Acknowledge from slave
Byte Count – 8 bits
Acknowledge from slave
Data byte 1 – 8 bits
Acknowledge from slave
Data byte 2 – 8 bits
Acknowledge from slave
Data Byte /Slave Acknowledges
Data Byte N – 8 bits
Acknowledge from slave
Stop
0 = Block read or block write operation, 1 = Byte read or byte write operation
Chip select address, set to ‘00’ to access device
Byte offset for byte read or byte write operation. For block read or block write operations, these bits should be '00000'
VDD_HTT
VSS_HTT
REF[2:0]
HTT66
Name
Block Write Protocol
O, SE 66 MHz clock output. Intel Type-5 buffer.
O, SE 14.318-MHz REF clock output. Intel Type-5 buffer.
PWR Ground for HyperTransport outputs
PWR 3.3V power supply for HyperTransport outputs
Type
Description
INFORMATION
ADVANCE
Description
Data Protocol
The clock driver serial protocol accepts byte write, byte read,
block write, and block read operations from the controller. For
block write/read operation, the bytes must be accessed in
sequential order from lowest to highest byte (most significant
bit first) with the ability to stop after any complete byte has
been transferred. For byte write and byte read operations, the
system controller can access individually indexed bytes. The
offset of the indexed byte is encoded in the command code,
as described in Table 1.
The block write and block read protocol is outlined in Table 2
while Table 3 outlines the corresponding byte write and byte
read protocol. The slave receiver address is 11010010 (D2h).
27:21
37:30
46:39
55:48
18:11
8:2
Bit
10
19
20
28
29
38
47
56
....
....
....
1
9
Description
Start
Slave address – 7 bits
Write
Acknowledge from slave
Command Code – 8 bits
Acknowledge from slave
Repeat start
Slave address – 7 bits
Read = 1
Acknowledge from slave
Byte Count from slave – 8 bits
Acknowledge
Data byte 1 from slave – 8 bits
Acknowledge
Data byte 2 from slave – 8 bits
Acknowledge
Data bytes from slave / Acknowledge
Data Byte N from slave – 8 bits
NOT Acknowledge
Block Read Protocol
Description
CY28RS680-2
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