cy28rs680 SpectraLinear Inc, cy28rs680 Datasheet - Page 11

• Manufacturer Part Number: cy28rs680
• Description: Clock Generator For Ati Rs5xx/6xx Chipsets
• Manufacturer: SpectraLinear Inc

Rev 1.0, March 28, 2007
Crystal Recommendations
The CY28RS680 requires a Parallel Resonance Crystal.
Substituting a series resonance crystal will cause the
CY28RS680 to operate at the wrong frequency and violate the
ppm specification. For most applications there is a 300-ppm
frequency shift between series and parallel crystals due to
incorrect loading.
Crystal Loading
Crystal loading plays a critical role in achieving low ppm perfor-
mance. To realize low ppm performance, the total capacitance
the crystal will see must be considered to calculate the appro-
priate capacitive loading (CL).
Figure 1
trim capacitors. An important clarification for the following
discussion is that the trim capacitors are in series with the
crystal not parallel. It is a common misconception that load
capacitors are in parallel with the crystal and should be
approximately equal to the load capacitance of the crystal.
This is not true.
Calculating Load Capacitors
In addition to the standard external trim capacitors, trace
capacitance and pin capacitance must also be considered to
correctly calculate crystal loading. As mentioned previously,
the capacitance on each side of the crystal is in series with the
crystal. This means the total capacitance on each side of the
crystal must be twice the specified crystal load capacitance
(CL). While the capacitance on each side of the crystal is in
series with the crystal, trim capacitors (Ce1,Ce2) should be
calculated to provide equal capacitive loading on both sides.
Use the following formulas to calculate the trim capacitor
values for Ce1 and Ce2.
CLe
shows a typical crystal configuration using the two
Total Capacitance (as seen by the crystal)
=
Figure 1. Crystal Capacitive Clarification
(
Load Capacitance (each side)
Ce1 + Cs1 + Ci1
Ce = 2 * CL – (Cs + Ci)
1
+
1
Ce2 + Cs2 + Ci2
1
)
CL....................................................Crystal load capacitance
CLe......................................... Actual loading seen by crystal
using standard value trim capacitors
Ce..................................................... External trim capacitors
Cs .............................................. Stray capacitance (terraced)
Ci ...........................................................Internal capacitance
(lead frame, bond wires etc.)
CLK_REQ[A:C]# Description
The CLKREQ#[A:C] signals are active LOW inputs used for
clean stopping and starting of selected SRC outputs. The
CLKREQ# signal is a debounced signal in that its state must
remain unchanged during two consecutive rising edges of
DIFC to be recognized as a valid assertion or deassertion.
(The assertion and deassertion of this signal is absolutely
asynchronous.)
CLK_REQ[A:C]# Assertion
The impact of asserting the CLKREQ#[A:C] pins is that all DIF
outputs that are set in the control registers to stoppable via
assertion of CLKREQ#[A:C] are to be stopped after their next
transition. The final state of all stopped DIF signals is tri-state;
both SRCT clock and SRCC clock outputs will be driven
tri-state.
CLK_REQ[A:C]# Deassertion
All differential outputs that were stopped are to resume normal
operation in a glitch free manner. The maximum latency from
the deassertion to active outputs is between 2 and 6 SRC
clock periods (2 clocks are shown) with all SRC outputs
resuming simultaneously.
Cs1
Ce1
Figure 2. Crystal Loading Example
X1
Ci1
Clock Chip
XTAL
Ci2
X2
Ce2
CY28RS680
Cs2
Page 11 of 20
3 to 6p
33 pF
Trim
Pin
2.8 pF
Trace