cy284108 SpectraLinear Inc, cy284108 Datasheet - Page 8

• Manufacturer Part Number: cy284108
• Description: Clock Generator For Intel Blackford And Bayshore Chipsets
• Manufacturer: SpectraLinear Inc

Rev 1.0, November 22, 2006
Table 5. Crystal Recommendations
The CY284108 requires a parallel resonance crystal. Substi-
tuting a series resonance crystal will cause the CY284108 to
operate at the wrong frequency and violate the ppm specifi-
cation. For most applications there is a 300-ppm frequency
shift between series and parallel crystals due to incorrect
loading.
Crystal Loading
Crystal loading plays a critical role in achieving low ppm perfor-
mance. To realize low ppm performance, the total capacitance
the crystal will see must be considered to calculate the appro-
priate capacitive loading (CL).
Figure shows a typical crystal configuration using the two trim
capacitors. An important clarification for the following
discussion is that the trim capacitors are in series with the
crystal not parallel. It is a common misconception that load
capacitors are in parallel with the crystal and should be
approximately equal to the load capacitance of the crystal.
This is not true.
Calculating Load Capacitors
In addition to the standard external trim capacitors, trace
capacitance and pin capacitance must also be considered to
correctly calculate crystal loading. As mentioned previously,
the capacitance on each side of the crystal is in series with the
crystal. This means the total capacitance on each side of the
crystal must be twice the specified crystal load capacitance
(CL). While the capacitance on each side of the crystal is in
series with the crystal, trim capacitors (Ce1,Ce2) should be
calculated to provide equal capacitive loading on both sides.
Figure 2.
14.31818 MHz
Frequency
(Fund)
Figure 1. Crystal Capacitive Clarification
Cut
AT
Loading Load Cap
Parallel
20 pF
0.1 mW
(max.)
Drive
Shunt Cap
Use the following formulas to calculate the trim capacitor
values for Ce1 and Ce2.
CL....................................................Crystal load capacitance
CLe......................................... Actual loading seen by crystal
using standard value trim capacitors
Ce..................................................... External trim capacitors
Cs .............................................. Stray capacitance (terraced)
Ci ...........................................................Internal capacitance
(lead frame, bond wires etc.)
PD (Power-down) Clarification
The VTT_PWRGD# /PD pin is a dual-function pin. During
initial power up, the pin functions as VTT_PWRGD#. Once
VTT_PWRGD# has been sampled low by the clock chip, the
pin assumes PD functionality. The PD pin is an asynchronous
active HIGH input used to shut off all clocks cleanly prior to
shutting off power to the device. This signal is synchronized
internal to the device prior to powering down the clock synthe-
sizer. PD is also an asynchronous input for powering up the
system. When PD is asserted high, drive all clocks to a low
value and hold prior to turning off the VCOs and the crystal
oscillator.
(max.)
Cs1
5 pF
CLe
Figure 3. Crystal Loading Example
Ce1
Total Capacitance (as seen by the crystal)
=
X1
Motional
0.016 pF
Ci1
(max.)
(
Clock Chip
Load Capacitance (each side)
Ce1 + Cs1 + Ci1
Ce = 2 * CL – (Cs + Ci)
XTAL
1
Tolerance
Ci2
35 ppm
(max.)
X2
Ce2
+
1
Ce2 + Cs2 + Ci2
Cs2
Stability
30 ppm
(max.)
3 to 6p
CY284108
33 pF
Pin
Trim
1
2.8 pF
Trace
Page 8 of 16
Aging
(max.)
5 ppm
)