cy28352oi-400t SpectraLinear Inc, cy28352oi-400t Datasheet - Page 2

• Manufacturer Part Number: cy28352oi-400t
• Description: Differential Clock Buffer/driver Ddr400 And Ddr333-compliant
• Manufacturer: SpectraLinear Inc

Rev 1.0, November 28, 2006
Pin Description
Zero Delay Buffer
When used as a zero delay buffer the CY28352-400 will likely
be in a nested clock tree application. For these applications
the CY28352-400 offers a clock input as a PLL reference. The
CY28352-400 can then lock onto the reference and translate
with near zero delay to low-skew outputs. For normal
operation, the external feedback input, FBIN, is connected to
the feedback output, FBOUT. By connecting the feedback
output to the feedback input the propagation delay through the
device is eliminated. The PLL works to align the output edge
with the input reference edge thus producing a near zero
delay. The reference frequency affects the static phase offset
of the PLL and thus the relative delay between the inputs and
outputs.
When A
bypassed for test purposes.
Function Table
Notes:
2,4,13,17,24,
1,5,14,16,25,
Pin Number Pin Name
1. A bypass capacitor (0.1μF) should be placed as close as possible to each positive power pin (< 0.2”). If these bypass capacitors are not close to the pins, their
2. Each output pair can be three-stated via the two-line serial interface.
9, 18, 21
high-frequency filtering characteristic will be cancelled by the lead inductance of the traces.
3,12,23
6,15,28
AVDD
GND
GND
20
26
27
19
22
10
11
2.5V
2.5V
2.5V
8
7
VDD
is strapped LOW, the PLL is turned off and
Inputs
CLKC(0:5)
CLKT(0:5)
FBOUT
SDATA
CLKIN
AGND
SCLK
AV
FBIN
GND
V
NC
[1]
DD
<20 MHz
DD
CLKIN
H
H
L
L
I/O
I/O
O
O
O
I
I
I
Complementary Clock Input.
Feedback Clock Input. Connect to FBOUT for accessing the PLL. Input
Clock Outputs
Clock Outputs
Feedback Clock Output. Connect to FBIN for normal operation.
A bypass delay capacitor at this output will control Input
Reference/Output Clocks phase relationships.
Serial Clock Input. Clocks data at SDATA into the internal
register.
Serial Data Input. Input data is clocked to the internal register to
enable/disable individual outputs. This provides flexibility in
power management.
2.6V Power Supply for Logic
2.6V Power Supply for PLL
Ground
Analog Ground for PLL
Not Connected
CLKT(0:5)
Hi-Z
H
H
L
L
[2]
CLKC(0:5)
Outputs
Pin Description
Hi-Z
H
H
L
L
Power Management
The
CY28352-400 allows the user to implement unique power
management schemes into the design. Outputs are
three-stated when disabled through the two-line interface as
individual bits are set low in Byte0 and Byte1 registers. The
feedback output FBOUT cannot be disabled via two line serial
bus. The enabling and disabling of individual outputs is done
in such a manner as to eliminate the possibility of partial “runt”
clocks.
[2]
individual
FBOUT
Hi-Z
H
H
L
L
output
enable/disable
Off
BYPASSED/OFF
BYPASSED/OFF
On
On
Input
Differential Outputs
Data Input for the two line
serial bus
Data Input and Output for
the two line serial bus
2.6V Nominal
2.6V Nominal
CY28352-400
Output
Characteristics
PLL
Electrical
control
Page 2 of 7
of
the