74LVTH273MTCX Fairchild Semiconductor, 74LVTH273MTCX Datasheet

IC FLIP FLOP OCT D LV 20TSSOP

74LVTH273MTCX

Manufacturer Part Number
74LVTH273MTCX
Description
IC FLIP FLOP OCT D LV 20TSSOP
Manufacturer
Fairchild Semiconductor
Series
74LVTHr
Type
D-Type Busr
Datasheet

Specifications of 74LVTH273MTCX

Function
Master Reset
Output Type
Non-Inverted
Number Of Elements
1
Number Of Bits Per Element
8
Frequency - Clock
150MHz
Delay Time - Propagation
4.9ns
Trigger Type
Positive Edge
Current - Output High, Low
32mA, 64mA
Voltage - Supply
2.7 V ~ 3.6 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
20-TSSOP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
74LVTH273MTCX
Manufacturer:
FSC
Quantity:
3 066
©1999 Fairchild Semiconductor Corporation
74LVTH273 Rev. 1.6.0
74LVTH273
Low Voltage Octal D-Type Flip-Flop with Clear
Features
Ordering Information
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering number.
Order Number
74LVTH273WM
74LVTH273SJ
74LVTH273MTC
Input and output interface capability to systems at
5V V
Bushold on the data inputs eliminate the need for
external pull-up resistors to hold unused inputs
Outputs source/sink –32mA/+64mA
Functionally compatible with the 74 series 273
Latch-up performance exceeds 500mA
ESD performance:
– Human-body model
– Machine model
– Charged-device model
All packages are lead free per JEDEC: J-STD-020B standard.
CC
Package
Number
200V
MTC20
M20D
M20B
2000V
1000V
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm
Wide
General Description
The LVTH273 is a high-speed, low-power positive-edge-
triggered octal D-type flip-flop featuring separate D-type
inputs for each flip-flop. A buffered Clock (CP) and Clear
(CLR) are common to all flip-flops.
The state of each D-type input, one setup time before
the positive clock transition, is transferred to the corre-
sponding flip-flop's output.
The LVTH273 data inputs include bushold, eliminating
the need for external pull-up resistors to hold unused
inputs.
These octal flip-flops are designed for low-voltage (3.3V)
V
interface to a 5V environment. The LVTH273 is fabri-
cated with an advanced BiCMOS technology to achieve
high speed operation similar to 5V ABT while maintain-
ing low power dissipation.
CC
Package Description
applications, but with the capability to provide a TTL
January 2008
www.fairchildsemi.com

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74LVTH273MTCX Summary of contents

Page 1

... MTC20 Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering number. All packages are lead free per JEDEC: J-STD-020B standard. ©1999 Fairchild Semiconductor Corporation 74LVTH273 Rev. 1.6.0 General Description The LVTH273 is a high-speed, low-power positive-edge- triggered octal D-type flip-flop featuring separate D-type inputs for each flip-flop ...

Page 2

... When the Clear (CLR) is LOW, all Outputs will be forced LOW. Logic Diagram Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. ©1999 Fairchild Semiconductor Corporation 74LVTH273 Rev. 1.6.0 Logic Symbols IEEE/IEC Truth Table ...

Page 3

... Symbol V Supply Voltage CC V Input Voltage I I HIGH-Level Output Current OH I LOW-Level Output Current OL T Free-Air Operating Temperature Input Edge Rate, V ©1999 Fairchild Semiconductor Corporation 74LVTH273 Rev. 1.6.0 Parameter , (1) Output in HIGH or LOW State GND I GND Parameter 0.8V–2.0V Rating – ...

Page 4

... An external driver must source at least the specified current to switch from LOW-to-HIGH external driver must sink at least the specified current to switch from HIGH-to-LOW. 5. This is the increase in supply current for each input that is at the specified voltage level rather than V ©1999 Fairchild Semiconductor Corporation 74LVTH273 Rev. 1.6.0 V ...

Page 5

... CLR HIGH before CP t Hold Time Data HIGH or LOW after CP H Note: 8. All typical values are (9) Capacitance Symbol Parameter C Input Capacitance IN C Output Capacitance OUT Note: 9. Capacitance is measured at frequency f ©1999 Fairchild Semiconductor Corporation 74LVTH273 Rev. 1.6.0 (6) Conditions V (V) C 50pF (7) 3.3 (7) 3 Min. 150 1 ...

Page 6

... Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifi ...

Page 7

... Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifi ...

Page 8

... Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifi ...

Page 9

... TRADEMARKS The following includes registered and unregistered trademarks and service marks, owned by Fairchild Semiconductor and/or its global subsidiaries, and is not intended exhaustive list of all such trademarks. ® ACEx Build it Now™ CorePLUS™ CROSSVOLT™ CTL™ Current Transfer Logic™ ...

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