ds1631a Maxim Integrated Products, Inc., ds1631a Datasheet - Page 12

• Manufacturer Part Number: ds1631a
• Description: High-precision Digital Thermometer And Thermostat
• Manufacturer: Maxim Integrated Products, Inc.

Figure 8. START, STOP, AND ACK SIGNALS
GENERAL 2-WIRE INFORMATION
INITIATING 2-WIRE COMMUNICATION
To initiate 2-wire communication, the master generates a START followed by a control byte containing
the DS1631, DS1631A, or DS1731 slave address. The R/
since the master next writes a command byte. The DS1631/DS1631A/DS1731 responds with an ACK
after receiving the control byte. This must be followed by a command byte from the master, which
indicates what type of operation is to be performed. The DS1631/DS1631A/DS1731 again respond with
an ACK after receiving the command byte.
If the command byte is a Start Convert T or Stop Convert T command (see Figure 9a), the transaction is
finished, and the master must issue a STOP to signal the end of the communication sequence. If the
command byte indicates a write or read operation, additional actions must occur as explained in the
following sections.
2-WIRE WRITES
The master can write data to the DS1631/DS1631A/DS1731 by issuing an Access Config, Access TH, or
Access TL command following the control byte (see Figures 9b and 9d). Since the R/
byte was a 0 (“write”), the DS1631/DS1631A/DS1731 are already prepared to receive data. Therefore,
after receiving an ACK in response to the command byte, the master device can immediately begin
transmitting data. When writing to the configuration register, the master must send one byte of data, and
when writing to the T
byte, the DS1631/DS1631A/DS1731 respond with an ACK, and the transaction is finished with a STOP
from the master.
All data is transmitted MSb first over the 2-wire bus.
One bit of data is transmitted on the 2-wire bus each SCL period.
A pullup resistor is required on the SDA line and, when the bus is idle, both SDA and SCL must remain
in a logic-high state.
All bus communication must be initiated with a START condition and terminated with a STOP
condition. During a START or STOP is the only time SDA is allowed to change states while SCL is
high. At all other times, changes on the SDA line can only occur when SCL is low: SDA must remain
stable when SCL is high.
After every 8-bit (1-byte) transfer, the receiving device must answer with an ACK (or NACK), which
takes one SCL period. Therefore, nine clocks are required for every one-byte data transfer.
SDA
SCL
H
or T
Condition
L
START
registers the master must send two bytes of data. After receiving each data
12 of 15
…
…
ACK (or NACK)
W ¯ ¯
From Receiver
bit of the control byte must be a 0 (“write”)
Condition
STOP
DS1631/DS1631A/DS1731
W ¯ ¯
bit in the control