ds1682st-r Maxim Integrated Products, Inc., ds1682st-r Datasheet - Page 14

• Manufacturer Part Number: ds1682st-r
• Description: Ds1682 Total-elapsed-time Recorder With Alarm
• Manufacturer: Maxim Integrated Products, Inc.

TIMING DIAGRAM
CHIP INFORMATION
TRANSISTOR COUNT: 26,032
PROCESS: CMOS
PACKAGE INFORMATION
(For the latest package information, go to www.maxim-ic.com/DallasPackInfo.)
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M a x i m I n t e g r a t e d P r o d u c t s , 1 2 0 S a n G a b r i e l D r i v e , S u n n y v a l e , C A 9 4 0 8 6 4 0 8 - 7 3 7 - 7 6 0 0
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Note 1:
Note 2:
Note 3:
Note 4:
Note 5:
Note 6:
Note 7:
Note 8:
Note 9:
Note 10:
Typical values are at +25°C, V
The elapsed time and event counters are backed by three EEPROM arrays, which are used
sequentially, allowing up to 3 x E
memory use a single array, limiting them to one E
A decoupling capacitor to supply high instantaneous currents during EEPROM writes is recommended.
A typical value is 0.01µF. V
EEPROM writes.
V
Reading data while the contents of EEPROM are transferred to RAM results in incorrect reads.
After this period, the first clock pulse is generated.
A device must internally provide a hold time of at least 300ns for the SDA signal (referred to the
V
The maximum t
signal.
A fast-mode device can be used in a standard-mode system, but the requirement t
be met. This is automatically the case if the device does not stretch the t
stretch t
before the SCL line is released.
C
B
CC
IHMIN
—total capacitance of one bus line in pF.
must be at or above 2.5V for t
of the SCL signal) to bridge the undefined region of the falling edge of SCL.
LOW
, it must output the next data bit to the SDA line t
HD:DAT
has only to be met if the device does not stretch the low period (t
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CC
CC
must be maintained above V
= 4.0V.
E
. The configuration register, alarm trip-point register and user
EW
after the end of an event to ensure data transfer to the EEPROM.
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E
.
DS1682 Total-Elapsed-Time Recorder with Alarm
CC
R(MAX)
minimum, including transients, during
+ t
SU:DAT
LOW
. If such a device does
= 1000 + 250 = 1250ns
SU:DAT
LOW
≥ 250ns must
) of the SCL