ds1876 Maxim Integrated Products, Inc., ds1876 Datasheet
ds1876
Available stocks
Related parts for ds1876
ds1876 Summary of contents
Page 1
... Rev 0; 2/10 SFP Controller with Dual LDD Interface General Description The DS1876 controls and monitors all functions for dual transmitter modules. The memory map is based on SFF-8472. The DS1876 supports APC and modula- tion control and eye safety functionality for two laser drivers ...
Page 2
SFP Controller with Dual LDD Interface Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
Page 3
SFP Controller with Dual LDD Interface TABLE OF CONTENTS (continued) Memory Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
Page 4
SFP Controller with Dual LDD Interface Figure 1. Power-Up Timing ...
Page 5
SFP Controller with Dual LDD Interface ABSOLUTE MAXIMUM RATINGS Voltage Range on PMON_, BMON_, RSEL, IN1, TXF_, and TXD_ Pins Relative to Ground ............................... -0. Voltage Range SDA, SCL, CC OUT1, RSELOUT, and TXFOUT Pins ...
Page 6
SFP Controller with Dual LDD Interface MOD_, APC_ ELECTRICAL CHARACTERISTICS (V = +2.85V to +3.9V -40NC to +95NC, unless otherwise noted PARAMETER SYMBOL Main Oscillator Frequency Delta-Sigma Input-Clock Frequency Reference Voltage Input (REFIN) V Output Range ...
Page 7
SFP Controller with Dual LDD Interface DIGITAL THERMOMETER CHARACTERISTICS (V = +2.85V to +3.9V -40NC to +95NC, unless otherwise noted PARAMETER SYMBOL Thermometer Error AC ELECTRICAL CHARACTERISTICS (V = +2.85V to +3.9V -40NC to ...
Page 8
SFP Controller with Dual LDD Interface NONVOLATILE MEMORY CHARACTERISTICS (V = +2.85V to +3.9V, unless otherwise noted.) CC PARAMETER EEPROM Write Cycles Note 1: All voltages are referenced to ground. Current into the IC is positive, and current out of ...
Page 9
SFP Controller with Dual LDD Interface (V = 3.3V +25°C, unless otherwise noted SUPPLY CURRENT vs. SUPPLY VOLTAGE 2.7 SDA = SCL = V CC DACs AT 1FFh 2.6 2.5 2.4 2.3 +25°C 2.2 2.1 2.0 ...
Page 10
... BMON2 and HBATH2 Quick Trip External Monitor Input PMON1 13 PMON1 and HTXP1/LTXP1 Quick Trip 10 _____________________________________________________________________________________ REFIN 22 TXD2 23 24 APC2 25 APC1 DS1876 TXF2 27 *EP + OUT1 THIN QFN (5mm 5mm 0.8mm) × × FUNCTION PIN ...
Page 11
... APC2 DAC SYSTEM STATUS/CONTROL BITS, 10 BITS ALARMS/WARNINGS, LOOKUP TABLES, USER MEMORY MOD1 DAC 10 BITS APC1 DAC 13-BIT 10 BITS ADC 8-BIT QTs POWER-ON ANALOG INTERRUPT V CC LOGIC CONTROL V CC DS1876 Block Diagram REFIN MOD2 APC2 MOD1 APC1 TXFOUT TXDOUT1 TXDOUT2 RSELOUT OUT1 GND 11 ...
Page 12
... Detailed Description The DS1876 integrates the control and monitoring func- tionality required in a dual transmitter system. Key com- ponents of the DS1876 are shown in the Block Diagram and described in subsequent sections. DACs During Power-Up On power-up, the DS1876 sets the DACs to high imped- ance ...
Page 13
... DS1876 already has deter- mined the present temperature, so the t required for the DS1876 to recall the APC and MOD set points from EEPROM. See Figure 1. DACs as a Function of Transmit Disable If TXD1 or TXD2 are asserted (logic 1) during normal ...
Page 14
... I customers with specified ADC ranges to calibrate the ADC full scale to a factor of 1/2 to measure small signals. The DS1876 can then right- shift the results by n bits to maintain the bit weight of their specification. LTXP1 ...
Page 15
... SFF-8472), then right- shifting can be used to adjust the PFS analog measure- ment range while maintaining the weighting of the ADC results. The DS1876’s range is wide enough to cover all requirements; when the maximum input value is P 1/2 the FS value, right-shifting can be used to obtain greater accuracy. For instance, the maximum voltage might be 1/8 the specified PFS value, so only 1/8 of the converter’ ...
Page 16
... DS1876 1k Ω 1k Ω DAC 0.1µF DS1876 Figure 6. Recommended RC Filter for DAC Outputs in Voltage Mode and Current Sink Mode For all device addresses sourced from EEPROM (Table 02h, Register 8Bh), the default device addresses are A2h and B2h until V exceeds POA allowing the device CC address to be recalled from the EEPROM ...
Page 17
SFP Controller with Dual LDD Interface Figure 7. 3-Bit (8-Position) Delta-Sigma Example DAC OFFSET LUTs (04h/06h)[A2h/B2h] EIGHT REGISTERS PER DAC EACH OFFSET REGISTER CAN BE INDEPENDENTLY 1023 SET BETWEEN 0 AND 1020. ...
Page 18
SFP Controller with Dual LDD Interface V CC TXDS_ R PU TXD_ TXDC_ TXP_ HI FLAG TXP HI ENABLE HBAL_ FLAG HBAL ENABLE QTHEXT_ TXP_ LO FLAG TXP LO ENABLE FAULT RESET TIMER (130ms) TXD (t ) EXT INITR1 OUT ...
Page 19
... TXFOUT. The CNFGB register (Table 02h, Register 89h) controls the latching of the alarms. Die Identification The DS1876 has an ID hardcoded in its memory. Two registers (Table 02h, Registers 86h-87h) are assigned for this feature. Register 86h reads 76h to identify the part as the DS1876; Register 87h reads the present device version ...
Page 20
... DS1876 assumes the master is communi- cating with another I munications until the next START condition is sent. Memory Address: During the DS1876, the master must transmit a memory address to identify the memory location where the slave is to store the data. The memory address is t ...
Page 21
... It is possible to take advantage of that phenomenon by repeatedly addressing the DS1876, which allows the next page to be written as soon as the DS1876 is ready to receive the data. The alternative to acknowledge polling is to wait for maximum period write again to the DS1876. ...
Page 22
... SFP Controller with Dual LDD Interface EEPROM Write Cycles: When EEPROM writes occur, the DS1876 writes the whole EEPROM memory page, even if only a single byte on the page was modified. Writes that do not modify all 8 bytes on the page are allowed and do not corrupt the remaining bytes of memory on the same page ...
Page 23
... Many nonvolatile memory locations (listed within the Register Descriptions section) are actually shadowed EEPROM and are controlled by the SEEB bit in Table 02h, Register 80h. The DS1876 incorporates shadowed EEPROM memory locations for key memory addresses that can be writ- ten many times. By default the shadowed EEPROM bit, ______________________________________________________________________________________ ...
Page 24
... There are a few registers that cannot be read without password access. The following access codes describe each mode used by the DS1876 with factory settings for the PW_ENA and PW_ENB (Table 02h, Registers C0h– C1h) registers. ...
Page 25
... BYTE 3 <D> <M> RESERVED ALARM EN 1 RESERVED <3/_> <4/_> <5/_> <6/_> All PW2 All N/A All and PW2 + DS1876 mode All All Hardware bit Lower Memory Register Map WORD 2 WORD 3 BYTE 4/C BYTE 5/D BYTE 6/E TEMP WARN HI TEMP WARN WARN WARN LO BMON WARN HI BMON WARN LO PMON WARN HI ...
Page 26
... MOD EMPTY EMPTY EMPTY MOD OFFSET MOD OFFSET MOD OFFSET LUT LUT LUT <3/_> <4/_> <5/_> <6/_> All PW2 All N/A All and PW2 + DS1876 mode All All Hardware bit Table 02h Register Map WORD 2 WORD 3 BYTE 4/C BYTE 5/D BYTE 6/E <10> RESERVED RESERVED DEVICE ID RANGING 2 RANGING 1 RSHIFT 2 RESERVED ...
Page 27
... AUXILIARY MEMORY (A0h) WORD 1 BYTE 1/9 BYTE 2/A BYTE 3 <3/_> <4/_> <5/_> <6/_> All PW2 All N/A All and PW2 + DS1876 mode All All Hardware bit Table 05h Register Map WORD 2 WORD 3 BYTE 4/C BYTE 5/D BYTE 6/E EMPTY EMPTY EMPTY <M> WARN EN 3 RESERVED RESERVED Table 06h Register Map WORD 2 ...
Page 28
SFP Controller with Dual LDD Interface Lower Memory, Register 00h–01h: TEMP ALARM HI Lower Memory, Register 04h–05h: TEMP WARN HI FACTORY DEFAULT READ ACCESS WRITE ACCESS A2h AND B2h MEMORY MEMORY TYPE 6 00h, 04h 01h, ...
Page 29
SFP Controller with Dual LDD Interface Lower Memory, Register 08h–09h: V Lower Memory, Register 0Ch–0Dh: V FACTORY DEFAULT READ ACCESS WRITE ACCESS A2h AND B2h MEMORY MEMORY TYPE 15 14 08h, 0Ch 09h, 0Dh 2 2 ...
Page 30
SFP Controller with Dual LDD Interface Lower Memory, Register 10h–11h: BMON ALARM HI Lower Memory, Register 14h–15h: BMON WARN HI Lower Memory, Register 18h–19h: PMON ALARM HI Lower Memory, Register 1Ch–1Dh: PMON WARN HI FACTORY DEFAULT READ ACCESS WRITE ACCESS ...
Page 31
SFP Controller with Dual LDD Interface Lower Memory, Register 20h–47h: EE FACTORY DEFAULT READ ACCESS WRITE ACCESS A2h AND B2h MEMORY MEMORY TYPE 20h–47h EE EE BIT 7 PW2 level access-controlled EEPROM. Lower Memory, Register 48h–57h: EE FACTORY DEFAULT READ ...
Page 32
SFP Controller with Dual LDD Interface Lower Memory, Register 60h–61h: TEMP VALUE FACTORY DEFAULT READ ACCESS WRITE ACCESS A2h AND B2h MEMORY MEMORY TYPE 6 60h 61h 2 2 BIT 7 Signed two’s complement direct-to-temperature measurement. ...
Page 33
SFP Controller with Dual LDD Interface Lower Memory, Register 64h–65h: BMON VALUE Lower Memory, Register 66h–67h: PMON VALUE POWER-ON VALUE READ ACCESS WRITE ACCESS A2h AND B2h MEMORY MEMORY TYPE 15 14 64h, 66h 65h, 67h ...
Page 34
SFP Controller with Dual LDD Interface Lower Memory, Register 6Eh: STATUS POWER-ON VALUE READ ACCESS WRITE ACCESS A2h AND B2h MEMORY MEMORY TYPE Write Access N/A All <D> <D> 6Eh TXDS TXDC BIT 7 TXDS1 [A2h]: TXD1 status bit. Reflects ...
Page 35
... These bits can be cleared so that a completion of a new conversion is verified. BITS 3:0 RESERVED ______________________________________________________________________________________ 00h All All and DS1876 hardware Different A2h and B2h memory locations Volatile BMON PMON RESERVED RDY RDY ...
Page 36
SFP Controller with Dual LDD Interface Lower Memory, Register 70h: ALARM POWER-ON VALUE READ ACCESS WRITE ACCESS A2h AND B2h MEMORY MEMORY TYPE 70h TEMP HI TEMP LO BIT 7 TEMP HI: High alarm status for temperature measurement. BIT 7 ...
Page 37
SFP Controller with Dual LDD Interface Lower Memory, Register 71h: ALARM POWER-ON VALUE READ ACCESS WRITE ACCESS A2h AND B2h MEMORY MEMORY TYPE 71h RESERVED RESERVED BIT 7 BITS 7:3 RESERVED TXFOUTS: TXFOUT status. Indicates the state the open-drain output ...
Page 38
SFP Controller with Dual LDD Interface Lower Memory, Register 73h: RESERVED POWER-ON VALUE READ ACCESS WRITE ACCESS A2h AND B2h MEMORY MEMORY TYPE This register is reserved. Lower Memory, Register 74h: WARN POWER-ON VALUE READ ACCESS WRITE ACCESS A2h AND ...
Page 39
... BIT 7 There are two passwords for the DS1876. Each password is 4 bytes long. The lower level password (PW1) has all the access of a normal user plus those made available with PW1. The higher level password (PW2) has all the access of PW1 plus those made available with PW2. The values of the passwords reside in EEPROM inside PW2 memory ...
Page 40
... BIT 7 The upper memory tables of the DS1876 are accessible by writing the desired table value in this register. The power-on value of this register is defined by the value written to TBLSELPON (Table 02h, Register C7h). Table 01h, Register 80h–F7h: EEPROM POWER-ON VALUE READ ACCESS ...
Page 41
SFP Controller with Dual LDD Interface Table 01h, Register F8h: ALARM EN POWER-ON VALUE READ ACCESS WRITE ACCESS A2h AND B2h MEMORY MEMORY TYPE <C> <C> F8h TEMP HI TEMP LO BIT 7 Layout is identical to ALARM Register 71h) ...
Page 42
SFP Controller with Dual LDD Interface Table 01h, Register F9h: RESERVED POWER-ON VALUE READ ACCESS WRITE ACCESS A2h AND B2h MEMORY MEMORY TYPE This register is reserved. Table 01h, Register FAh: ALARM EN POWER-ON VALUE READ ACCESS WRITE ACCESS A2h ...
Page 43
SFP Controller with Dual LDD Interface Table 01h, Register FCh: WARN EN POWER-ON VALUE READ ACCESS WRITE ACCESS A2h AND B2h MEMORY MEMORY TYPE <C> <C> FCh TEMP HI TEMP LO BIT 7 Layout is identical to WARN Register 71h) ...
Page 44
SFP Controller with Dual LDD Interface Table 01h, Register FDh–FFh: RESERVED POWER-ON VALUE READ ACCESS WRITE ACCESS A2h AND B2h MEMORY MEMORY TYPE These registers are reserved. Table 02h, Register 80h: MODE POWER-ON VALUE READ ACCESS WRITE ACCESS A2h AND ...
Page 45
SFP Controller with Dual LDD Interface Table 02h, Register 80h: MODE (continued) MOD1EN MOD1 DAC is writable by the user and the LUT recalls are disabled. This allows the user to BIT 2 interactively test their modules by ...
Page 46
SFP Controller with Dual LDD Interface Table 02h, Register 82h–85h: RESERVED FACTORY DEFAULT READ ACCESS WRITE ACCESS A2h AND B2h MEMORY MEMORY TYPE These registers are reserved. Table 02h, Register 86h: DEVICE ID FACTORY DEFAULT READ ACCESS WRITE ACCESS MEMORY ...
Page 47
SFP Controller with Dual LDD Interface Table 02h, Register 88h: CNFGA FACTORY DEFAULT READ ACCESS WRITE ACCESS A2h AND B2h MEMORY MEMORY TYPE 88h QTHEXT2 QTHEXT1 BIT 7 QTHEXT2: QT high extension for transmitter Disabled. TXP HI ...
Page 48
SFP Controller with Dual LDD Interface Table 02h, Register 89h: CNFGB FACTORY DEFAULT READ ACCESS WRITE ACCESS A2h AND B2h MEMORY MEMORY TYPE 89h IN1C INVOUT1 BIT 7 IN1C: IN1 software control bit (see Figure 10). BIT ...
Page 49
SFP Controller with Dual LDD Interface Table 02h, Register 8Ah: CNFGC FACTORY DEFAULT READ ACCESS WRITE ACCESS A2h AND B2h MEMORY MEMORY TYPE 8Ah TXDFG2 TXDFLT2 BIT 7 TXDFG2: See Figure 9. BIT FETG2, an internal signal, ...
Page 50
SFP Controller with Dual LDD Interface Table 02h, Register 8Ch: RANGING FACTORY DEFAULT READ ACCESS WRITE ACCESS A2h AND B2h MEMORY MEMORY TYPE 8Ch RESERVED HBIAS2 BIT 7 The upper nibble of this byte controls the full-scale range of the ...
Page 51
SFP Controller with Dual LDD Interface Table 02h, Register 8Dh: RANGING FACTORY DEFAULT READ ACCESS WRITE ACCESS A2h AND B2h MEMORY MEMORY TYPE 8Dh RESERVED HBIAS1 BIT 7 The upper nibble of this byte controls the full-scale range of the ...
Page 52
SFP Controller with Dual LDD Interface Table 02h, Register 8Eh: RIGHT-SHIFT FACTORY DEFAULT READ ACCESS WRITE ACCESS A2h AND B2h MEMORY MEMORY TYPE 8Eh RESERVED BMON2 2 BIT 7 Allows for right-shifting the final answer of BMON2 and PMON2 voltage ...
Page 53
SFP Controller with Dual LDD Interface Table 02h, Register 92h–93h Table 02h, Register 94h–97h: RESERVED Table 02h, RegisteR 98h–99h: BMON2 SCALE Table 02h, Register 9Ah–9Bh: PMON2 SCALE Table 02h, Register 9Ch–9Dh: BMON1 SCALE Table 02h, Register 9Eh–9Fh: PMON1 ...
Page 54
SFP Controller with Dual LDD Interface Table 02h, Register A2h–A3h Table 02h, Register A4h–A7h: RESERVED Table 02h, Register A8h–A9h: BMON2 OFFSET Table 02h, Register AAh–ABh: PMON2 OFFSET Table 02h, Register ACh–ADh: BMON1 OFFSET Table 02h, Register AEh–AFh: PMON1 ...
Page 55
SFP Controller with Dual LDD Interface Table 02h, Register B4h–B7h: PW2 FACTORY DEFAULT READ ACCESS WRITE ACCESS MEMORY TYPE 31 30 B4h B5h B6h B7h 2 2 BIT ...
Page 56
SFP Controller with Dual LDD Interface Table 02h, Register BAh: HTXP2 DAC FACTORY DEFAULT READ ACCESS WRITE ACCESS A2h AND B2h MEMORY MEMORY TYPE 7 6 BAh 2 2 BIT 7 The digital value used for the HTXP2 reference and ...
Page 57
SFP Controller with Dual LDD Interface Table 02h, Register BDh: HBIAS1 DAC FACTORY DEFAULT READ ACCESS WRITE ACCESS A2h AND B2h MEMORY MEMORY TYPE 7 6 BDh 2 2 BIT 7 The digital value used for the HBIAS1 reference and ...
Page 58
SFP Controller with Dual LDD Interface Table 02h, Register C0h: PW_ENA FACTORY DEFAULT READ ACCESS WRITE ACCESS A2h AND B2h MEMORY MEMORY TYPE C0h RESERVED RWTBL1C BIT 7 BIT 7 RESERVED RWTBL1C: Table 01h or 05h bytes F8–FFh. Table address ...
Page 59
SFP Controller with Dual LDD Interface Table 02h, Register C1h: PW_ENB FACTORY DEFAULT READ ACCESS WRITE ACCESS A2h AND B2h MEMORY MEMORY TYPE C1h RWTBL46 RTBL1C BIT 7 RWTBL46: Tables 04h and 06h. BIT (default) Read and ...
Page 60
SFP Controller with Dual LDD Interface Table 02h, Register C6h: POLARITY FACTORY DEFAULT READ ACCESS WRITE ACCESS A2h AND B2h MEMORY MEMORY TYPE C6h RESERVED RESERVED BIT 7 BITS 7:4 RESERVED MOD2P: MOD2 DAC polarity. The MOD2 DAC (Table 02h, ...
Page 61
SFP Controller with Dual LDD Interface Table 02h, Register C7h: TBLSELPON FACTORY DEFAULT READ ACCESS WRITE ACCESS A2h AND B2h MEMORY MEMORY TYPE 7 6 C7h 2 2 BIT 7 Chooses the initial value for the TBL SEL byte (Lower ...
Page 62
SFP Controller with Dual LDD Interface Table 02h, Register CAh–CBh: APC2 DAC FACTORY DEFAULT READ ACCESS WRITE ACCESS A2h AND B2h MEMORY MEMORY TYPE CAh CBh 2 2 BIT 7 The digital value used for APC2 ...
Page 63
SFP Controller with Dual LDD Interface Table 02h, Register CEh–CFh: APC1 DAC FACTORY DEFAULT READ ACCESS WRITE ACCESS A2h AND B2h MEMORY MEMORY TYPE CEh CFh 2 2 BIT 7 The digital value used for APC1 ...
Page 64
SFP Controller with Dual LDD Interface Table 04h, Register 80h–C7h: MODULATION LUT (MOD) FACTORY DEFAULT READ ACCESS WRITE ACCESS A2h AND B2h MEMORY MEMORY TYPE 7 6 80h–C7h 2 2 BIT 7 Digital value for the MOD1 DAC (A2h address) ...
Page 65
SFP Controller with Dual LDD Interface Table 04h, Register F8h–FFh: MOD OFFSET LUT FACTORY DEFAULT READ ACCESS WRITE ACCESS A2h AND B2h MEMORY MEMORY TYPE 9 F8h–FFh 2 2 BIT 7 The digital value for the temperature offset of the ...
Page 66
SFP Controller with Dual LDD Interface Table 06h, Register C8h–DFh: EMPTY FACTORY DEFAULT READ ACCESS WRITE ACCESS A2h AND B2h MEMORY MEMORY TYPE These registers do not exist. Table 06h, Register E0h–E7h: HBATH LUT FACTORY DEFAULT READ ACCESS WRITE ACCESS ...
Page 67
SFP Controller with Dual LDD Interface Table 06h, Register E8h–EFh: HTXP LUT FACTORY DEFAULT READ ACCESS WRITE ACCESS A2h AND B2h MEMORY MEMORY TYPE 7 E8h–EFh 2 2 BIT 7 The HTXP LUT is used to temperature compensate the transmit ...
Page 68
SFP Controller with Dual LDD Interface Table 06h, Register F8h–FFh: APC OFFSET LUT FACTORY DEFAULT READ ACCESS WRITE ACCESS A2h AND B2h MEMORY MEMORY TYPE 9 F8h–FFh 2 2 BIT 7 The digital value for the temperature offset of the ...
Page 69
... GND pins to minimize lead inductance. CC SDA and SCL Pullup Resistors SDA is an open-collector output on the DS1876 that requires a pullup resistor to realize high logic levels. A master using either an open-collector output with a pul- lup resistor or a push-pull output driver can be used for SCL ...