ds1843 Maxim Integrated Products, Inc., ds1843 Datasheet - Page 7

• Manufacturer Part Number: ds1843
• Description: Rssi Burst-mode Sample-and-hold Circuit In 2mm X 2mm ?dfn Package
• Manufacturer: Maxim Integrated Products, Inc.

Figure 1. Input Impedances for Settling Time Calculations Diagram
To achieve the best results when using the DS1843,
decouple the power-supply pin, V
0.1μF capacitor. Use a high-quality X7R or equivalent
ceramic surface-mount capacitor.
The settling time is dependent on the gain ratio of the
current mirror used at the input of the DS1843. For
example, the MAX4007 includes a 10:1 ratio current
mirror. This requires a 5kΩ resistor to create a 1V full-
scale output with 2mA current input to the MAX4007.
This resistor can be decreased to 2.5kΩ by using the
DS1842, which has a 5:1 ratio current mirror.
Variable Definitions:
R
across this resistor.
R
circuitry to input pins after t
C
C
output and typical trace capacitance are less than
10pF.
C
t
trical specification. The minimum t
constant. t
t
IST
RC
IN
SW
IN
PAR
S
: 5pF sample capacitor.
: RC settling time of the input.
: Input resistor. The current mirror creates a voltage
: Internal settling time based on t
: 7pF parasitic (ESD) capacitor.
: Resistance of series switch that connects internal
: External parasitic capacitance. A current mirror's
IST
DS1843 Estimated Settling Time
removes this time constant.
Applications Information
_______________________________________________________________________________________
MIRROR OUTPUT
Power-Supply Decoupling
CURRENT
IST
C
PAR
time.
CC
S
S
includes one time
, with a 0.01μF or
R
from the AC elec-
IN
Fast Sample-and-Hold Circuit
V
V
INP
INN
C
C
IN
IN
Figure 1 shows the simplified diagram of input imped-
ances for settling time calculations. Sample time is
divided into two parts:
1) t
2) t
Example:
Approximate accuracy calculations can be done for an
input voltage based on the above impedance values.
These calculations can be divided into three parts.
1) Accuracy of input at t
V
IN t
R
R
@
SW
SW
time, voltage V
stant of:
a. Input V
to its final value with a new time constant of:
b. R
stant of R
where t
At t
This causes charge redistribution to occur, which
causes a dip in the input voltage. The worst-case
value of the input voltage at t
IST
RC
IST
: Internal settling time (max 250ns). During this
: During this period two things happen:
⎧
⎨
⎩
IST
SW
=
INPUT MODEL
(
R
Accuracy
⎡
⎢
⎢
⎣
DS1843
1
IN
1
and C
the internal circuit tags input impedance.
−
= t
(
SW
×
IN
C
IN
(
IST
C
C
C
keeps increasing from its value at t
x C
S
S
+
S
IN
R
C
IN
= 250ns.
track this V
C
IN
PAR
S
= −
+
S
(V
, which is 12.5ns (worst case).
1
C
x (C
INP
+
PAR
C
IST
e
S
IN
- V
⎡
⎣
)
R
)
⎤
⎥
⎥
⎦
(250ns):
+ C
)
IN
×
INN
2
IN
⎡
⎢
⎢
⎢
⎢
⎣
×
1
+
(
IST
−
PAR
(input) with a time con-
C
) rises with a time con-
(
e
R
−
IN
⎡
⎣
t
SW
is:
R R
1
+
)
IN
C
×
PAR
(
×
C
−
t
IN
C
IST
+
)
S
⎤
⎦
C
)
PAR
2
⎫
⎬
⎭
)
⎤
⎦
⎤
⎥
⎥
⎥
⎥
⎦
×
V
IST
IN
7