74LVQ273SJ Fairchild Semiconductor, 74LVQ273SJ Datasheet

74LVQ273SJ

Manufacturer Part Number

74LVQ273SJ

Description

IC FLIP FLOP OCT D LV 20-SOP

Manufacturer

Fairchild Semiconductor

Series

74LVQr

Type

D-Type Busr

Datasheet

1.74LVQ273SJX.pdf (6 pages)

Specifications of 74LVQ273SJ

Function

Master Reset

Output Type

Non-Inverted

Number Of Elements

Number Of Bits Per Element

Frequency - Clock

90MHz

Delay Time - Propagation

8ns

Trigger Type

Positive Edge

Current - Output High, Low

12mA, 12mA

Voltage - Supply

2 V ~ 3.6 V

Operating Temperature

-40°C ~ 85°C

Mounting Type

Surface Mount

Package / Case

20-SOIC (5.3mm Width), 20-SO, 20-SOEIAJ

Lead Free Status / RoHS Status

Lead free / RoHS Compliant

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74LVQ273SC

74LVQ273SJ

74LVQ273QSC

74LVQ273

Low Voltage Octal D-Type Flip-Flop

General Description

The LVQ273 has eight edge-triggered D-type flip-flops with

individual D inputs and Q outputs. The common buffered

Clock (CP) and Master Reset (MR) input load and reset

(clear) all flip-flops simultaneously.

The register is fully edge-triggered. The state of each D

input, one setup time before the LOW-to-HIGH clock transi-

tion, is transferred to the corresponding flip-flop’s Q output.

All outputs will be forced LOW independently of Clock or

Data inputs by a LOW voltage level on the MR input. The

device is useful for applications where the true output only

is required and the Clock and Master Reset are common to

all storage elements.

Ordering Code:

Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.

Logic Symbols

Order Number

Package Number

IEEE/IEC

MQA20

M20B

M20D

20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide

20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide

20-Lead Quarter Size Outline Package (QSOP), JEDEC MO-137, 0.150" Wide

DS011358

Features

Connection Diagram

Pin Descriptions

Ideal for low power/low noise 3.3V applications

Implements patented EMI reduction circuitry

Available in SOIC JEDEC, SOIC EIAJ and QSOP

packages

Guaranteed simultaneous switching noise level and

dynamic threshold performance

Improved latch-up immunity

Guaranteed incident wave switching into 75

4 kV minimum ESD immunity

Package Description

Pin Names

–D

–Q

Data Inputs

Master Reset

Clock Pulse Input

Data Outputs

February 1992

Revised June 2001

Description

www.fairchildsemi.com

Related parts for 74LVQ273SJ

74LVQ273SJ Summary of contents

Page 1

... Ordering Code: Order Number Package Number 74LVQ273SC M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide 74LVQ273SJ M20D 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 74LVQ273QSC MQA20 20-Lead Quarter Size Outline Package (QSOP), JEDEC MO-137, 0.150" Wide Devices also available in Tape and Reel. Specify by appending suffix letter “ ...

Page 2

Absolute Maximum Ratings Supply Voltage ( Input Diode Current ( 0. 0. Input Voltage ( Output Diode Current ( ...

Page 3

AC Electrical Characteristics Symbol Parameter f Maximum Clock MAX Frequency t Propagation Delay PLH Propagation Delay PHL Propagation Delay PHL Output to Output OSHL t ...

Page 4

Physical Dimensions inches (millimeters) unless otherwise noted 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide www.fairchildsemi.com Package Number M20B 4 ...

Page 5

Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide Package Number M20D 5 www.fairchildsemi.com ...

Page 6

Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 20-Lead Quarter Size Outline Package (QSOP), JEDEC MO-137, 0.150" Wide Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the ...

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