upd75238 Renesas Electronics Corporation., upd75238 Datasheet - Page 131
upd75238
Manufacturer Part Number
upd75238
Description
4 Bit Single-chip Microcomputer
Manufacturer
Renesas Electronics Corporation.
Datasheet
1.UPD75238.pdf
(190 pages)
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5. INTERRUPT FUNCTION
input.
(a) Vector interrupt function under hardware control which can determine whether to accept an interrupt by
(b) Any interrupt start address can be set.
(c) Multiple interrupt function which can specify the priority by the interrupt priority specification register
(d) Test function of an interrupt request flag (IRQ
(e) Release of the standby mode (Interrupts released by an interrupt enable flag can be selected.)
5.1 CONFIGURATION OF THE INTERRUPT CONTROL CIRCUIT
mapped in the data memory space.
INTBT
INT4
INT0
INT1
INTCSI0
INTT0
INTTPG
INTKS
INT2
INTW
The PD75238 has eight interrupt sources and can handle multiple interrupts with a priority.
The PD75238 is also provided with two test sources. One test source, INT2, is set by edge detection testable
Notes 1. The priority is used when two or more interrupt requests are issued at a time.
The following functions are provided for the interrupt control circuit of the PD75238.
The interrupt control circuit of the PD75238 is configured as shown in Fig. 5-1. Each hardware item is
an interrupt enable flag (IE
(IPS)
(The software can confirm that an interrupt occurred.)
Note 2
Note 2
2. INT2 and INTW are test sources. Like interrupt sources, these test sources are controlled by an
(Reference time interval signal from basic
interval timer)
(Detection of rising or falling edge)
(Rising/falling edge detection specification)
(Serial data transfer completion signal)
(Match signal from timer enter/counter 0)
(Match signal from timer/pulse generator)
(Key scan timing signal from display controller)
(Detection of rising edge )
(Signal from clock timer)
interrupt enable flag. But, they do not cause vector interrupts.
Interrupt source
) and the interrupt master enable flag (IME)
Table 5-1 Interrupt Sources
)
In/out
Out
Out
Out
Out
In
In
In
In
In
In
Testable input signal (Sets IRQ2 and IRQW.)
Priority
1
2
3
4
5
6
7
Note 1
Vector interrupt request
signal (vector table
address)
VRQ5 (000AH)
VRQ6 (000CH)
VRQ7 (000EH)
VRQ1 (0002H)
VRQ2 (0004H)
VRQ3 (0006H)
VRQ4 (0008H)
PD75238
131
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