rs5c338a RICOH Co.,Ltd., rs5c338a Datasheet - Page 15

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rs5c338a

Manufacturer Part Number
rs5c338a
Description
3-wire Serial Interface Real-time Clock Ics With Voltage Monitoring Function
Manufacturer
RICOH Co.,Ltd.
Datasheet

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2.2-7 WAFG and DAFG
The WAFG and DAFG bits are valid only when the WALE and DALE bits have the setting of 1, which is caused
approximately 61µs after any match between current time and preset alarm time specified by the Alarm_W registers
and the Alarm_D registers. The WAFG and DAFG bits accept only the writing of 0, which disables (“H”) the INTR
pin until it is enabled (“L”) again at the next preset alarm time. Conversely, setting the WAFG and DAFG bits to 1
causes no event. The WAFG and DAFG bits will have the reading of 0 when the alarm interrupt circuit is disabled
with the WALE and DALE bits set to 0. The settings of the WAFG and DAFG bits are synchronized with the output
of the INTR pin as shown in the timing chart below.
Output Relationships Between the WAFG or DAFG Bit and INTR
WAFG, DAFG
Settings of WAFG (DAFG) bit
0
1
Output of INTR pin
Alarm_W Flag Bit and Alarm_D Flag Bit
Indicating a mismatch between current time and preset alarm time
Indicating a match between current time and preset alarm time
(Match between current time
and preset alarm time)
Writing of 0 to WAFG
(DAFG) bit
Approx. 61µs
(Match between current time
and preset alarm time)
Description
Approx. 61µs
(Match between current time
and preset alarm time)
Writing of 0 to WAFG
(DAFG) bit
(Default setting)
R
×
5C338A
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