mx1ds10p Centellax, mx1ds10p Datasheet - Page 4

• Manufacturer Part Number: mx1ds10p
• Description: 15 Ghz Ultra - Variable Broadband Prescaler
• Manufacturer: Centellax

Application Notes
Low Frequency Operation
Low frequency operation is limited by external bypass capacitors and the slew rate of the input clock. The next
paragraph shows the calculations for the bypass capacitors. If DC coupled, the device operates down to DC for
square-wave inputs. Sine-wave inputs are limited to ~50MHz due to the 10dBm max input power limitation.
The values of the coupling capacitors for the high-speed inputs and outputs (I/O’s) is determined by the lowest
frequency the IC will be operated at.
For example to use the device below 30kHz, coupling capacitors should be larger than 0.1uF.
IC Assembly
The device is designed to operate with either single-ended or differential inputs. Figures 1, 2 & 3 show the IC
assembly diagrams for positive and negative supply voltages. In either case the supply should be capacitively
bypassed to the ground to provide a good AC ground over the frequency range of interest. The backside of the
chip should be connected to a good thermal heat sink.
All RF I/O’s are connected to VCC through on-chip termination resistors. This implies that when Vcc is not DC
grounded (as in the case of positive supply), the RF I/O’s should be AC coupled through series capacitors unless
the connecting circuit can generate the correct levels through level shifting.
ESD Sensitivity
Although SiGe IC’s have robust ESD sensitivities, preventive ESD measures should be taken while storing,
handling, and assembling.
Inputs are more ESD susceptible as they could expose the base of a BJT or the gate of a MOSFET. For this
reason, all the inputs are protected with ESD diodes. These inputs have been tested to withstand voltage
spikes up to 400V.
Negative CML Logic Levels for DC Coupling (T=25 ºC)
Assuming 50Ω Terminations at Inputs and Outputs
Differential
Differential
Single
Single
Parameter
&
Specifications subject to change without notice. Copyright © 2001-2009 Centellax, Inc. Printed in USA. 15 Jun 2009. smd-00028 rev C.
CENTELLAX
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Logic Input
Logic Input
Logic Input
Logic Input
Logic Output
Logic Output
high
low
high
low
high
low
C>>
Vcc - 0.05V
Vcc + 0.05V
Vcc - 0.05V
Vcc - 0.2V
Minimum
MX1DS10P: PAGE 4 of 8
Vcc
Vcc
2
.
π
.
50Ω
1
.
f
lowest
Vcc - 0.3V
Vcc + 0.3V
Vcc - 0.3V
Vcc - 0.3V
Typical
Vcc
Vcc
Vcc - 1V
Vcc + 1V
Vcc - 1V
Vcc - 0.4V
Maximum
Vcc
Vcc